An Efficient Denoising Architecture for

Removal of Impulse Noise in Images

Chih-Yuan Lien, Chien-Chuan Huang, Pei-Yin Chen, Member, IEEE, and Yi-Fan Lin
AbstractImages are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we
propose an efficient denoising scheme and its VLSI architecture for the removal of random-valued impulse noise. To achieve the goal
of low cost, a low-complexity VLSI architecture is proposed. We employ a decision-tree-based impulse noise detector to detect the
noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels. Furthermore, an adaptive technology is
used to enhance the effects of removal of impulse noise. Our extensive experimental results demonstrate that the proposed technique
can obtain better performances in terms of both quantitative evaluation and visual quality than the previous lower complexity methods.
Moreover, the performance can be comparable to the higher complexity methods. The VLSI architecture of our design yields a
processing rate of about 200 MHz by using TSMC 0.18 m technology. Compared with the state-of-the-art techniques, this work can
reduce memory storage by more than 99 percent. The design requires only low computational complexity and two line memory buffers.
Its hardware cost is low and suitable to be applied to many real-time applications.
Index TermsImage denoising, impulse noise, impulse detector, architecture

1 INTRODUCTION
I
MAGE processing is widely used in many fields, such as
medical imaging, scanning techniques, printing skills,
license plate recognition, face recognition, and so on. In
general, images are often corrupted by impulse noise in
the procedures of image acquisition and transmission. The
noise may seriously affect the performance of image
processing techniques. Hence, an efficient denoising tech-
nique becomes a very important issue in image processing
[1], [2]. According to the distribution of noisy pixel values,
impulse noise can be classified into two categories: fixed-
valued impulse noise and random-valued impulse noise.
The former is also known as salt-and-pepper noise because
the pixel value of a noisy pixel is either minimum or
maximum value in gray-scale images. The values of noisy
pixels corrupted by random-valued impulse noise are
uniformly distributed in the range of [0, 255] for gray-scale
images. There have been many methods for removing salt-
and-pepper noise, and some of them perform very well [3],
[4], [5], [6], [7]. The random-valued impulse noise is more
difficult to handle due to the random distribution of noisy
pixel values. We only focus on removing the random-valued
impulse noise from the corrupted image in this paper.
Recently, many image denoising methods have been
proposed to carry out impulse noise suppression [8], [9], [10],
[11], [12], [13], [14], [15], [16], [17], [18]. Some of thememploy
the standard median filter [8] or its modifications [9], [10].
However, these approaches might blur the image since both
noisy and noise-free pixels are modified. To avoid the
damage on noise-free pixels, an efficient switching strategy
has been proposed in the literature [11], [12], [13]. In general,
the switching median filter consists of two steps: 1) impulse
detection and 2) noise filtering. It locates the noisy pixels
with an impulse detector, and then filters them rather than
the whole pixels of an image to avoid causing the damage on
noise-free pixels. In addition to median filer, there are other
methods used to carry out impulse noise. In [14], Luo
proposed an alpha-trimmed mean-based method (ATMBM).
It used the alpha-trimmed mean in impulse detection and
replaced the noisy pixel value by a linear combination of its
original value and the median of its local window. A
differential rank impulse detector (DRID) was presented in
[15]. The impulse detector of DRID is based on a comparison
of signal samples within a narrowrank windowby both rank
and absolute value. In [16], Yu et al. proposed a method
using a statistic of rank-ordered relative differences (RORD-
WMF) to identify pixels which are likely to be corrupted by
impulse noise. A directional weighted median (DWM)
method proposed by Dong and Xu was presented in [17].
It is based on the differences between the current pixel and
its neighbors aligned with four main directions. In [18],
Petrovic and Crnojevic proposed a method that employed
genetic programming for impulse noise filter construction.
The method is based on the switching scheme with cascaded
detectors and corresponding estimators.
Generally, the denoising methods can be classified into
two categories: lower complexity techniques [8], [9], [10],
[11], [12], [13] and higher complexity techniques [14], [15],
[16], [17], [18]. The complexity of denoising algorithms
IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013 631
. C.-Y. Lien is with the Department of Electronic Engineering, National
Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan, R.O.C.
E-mail: [email protected].
. C.-C. Huang, P.-Y. Chen, and Y.-F. Lin are with the Department of
Computer Science and Information Engineering, National Cheng Kung
University, No. 1, Ta-Hsueh Road, Tainan 70101, Taiwan, R.O.C.
E-mail: [email protected], [email protected],
[email protected].
Manuscript received 7 June 2011; revised 26 Oct. 2011; accepted 20 Dec.
2011; published online 27 Dec. 2011.
Recommended for acceptance by L. Wang.
For information on obtaining reprints of this article, please send e-mail to:
[email protected], and reference IEEECS Log Number TC-2011-06-0379.
Digital Object Identifier no. 10.1109/TC.2011.256.
0018-9340/13/$31.00 2013 IEEE Published by the IEEE Computer Society
depends mainly on the local window size, memory buffer,
and iteration times. The lower complexity techniques use a
fixed-size local window, require a few line buffers, and
perform no iterations. Therefore, the computational com-
plexity is low. However, the reconstructed image quality is
not good enough. The higher complexity techniques yield
visually pleasing images by using high computational
complexity arithmetic operations, enlarging local window
size adaptively or doing iterations. The higher complexity
approaches require long computational time as well as full
frame buffer. Today, in many practical real-time applica-
tions, the denoising process is included in end-user
equipment, so there appears an increasing need of a good
lower-complexity denoising technique, which is simple and
suitable for low-cost VLSI implementation. Low cost is a
very important consideration in purchasing consumer
electronic products. To achieve the goal of low cost, less
memory and easier computations are indispensable. In this
paper, we focus only on the lower complexity denoising
techniques because of its simplicity and easy implementa-
tion with the VLSI circuit.
The decision tree is a simple but powerful form of
multiple variable analysis [19]. It can break down a complex
decision-making process into a collection of simpler
decisions, thus provide a solution which is often easier to
interpret [20]. There have been several methods using
decision tree to deal with salt-and-pepper noise [4], [5], [21],
[22], [23], [37] and some of them perform well.
Based on above basic concepts, we present a novel
adaptive decision-tree-based denoising method (DTBDM)
and its VLSI architecture for removing random-valued
impulse noise. To enhance the effects of removal of impulse
noise, the results of reconstructed pixels are adaptively
written back as a part of input data. The proposed design
requires simple computations and two line memory buffers
only, so its hardware cost is low. For a 512 512 8-bit gray-
scale test image, only two line buffer 512 2 8 bits is
needed in our design. Most state-of-the-art methods need to
buffer a full image 512 512 8 bits. In our design,
99.6 percent of storage is reduced. Furthermore, only simple
arithmetic operations, such as addition and subtraction, are
used in DTBDM. Especially, it can remove the noise from
corrupted images efficiently and requires no previous
training. Our extensive experimental results demonstrate
that the proposed technique can obtain better performances
in terms of both quantitative evaluation and visual quality
than other lower complexity denoising methods [8], [9],
[10], [11], [12], [13]. Moreover, the performance can be
comparable to the higher complexity methods [14], [15],
[16]. The seven-stage VLSI architecture for the proposed
design was implemented and synthesized by using Verilog
HDL and Synopsys Design Compiler, respectively. In our
simulation, the circuit can achieve 200 MHz with only 21k
gate counts by using TSMC 0:18 m technology.
The rest of this paper is organized as follows. The
proposed DTBDM is introduced briefly in Section 2.
Section 3 describes the proposed VLSI architecture in detail.
Section 4 illustrates the VLSI implementation and compar-
isons. The conclusion is provided in Section 5.
2 THE PROPOSED DTBDM
The noise considered in this paper is random-valued
impulse noise with uniform distribution as practiced in
[8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18]. Here,
we adopt a 3 3 mask for image denoising. Assume the
pixel to be denoised is located at coordinate i; j and
denoted as p
i;j
, and its luminance value is named as f
i;j
, as
shown in Fig. 1. According to the input sequence of image
denoising process, we can divide other eight pixel values
into two sets: W
TopHalf
and W
BottomHalf
. They are given as
W
TopHalf
fa; b; c; dg: 1
W
BottomHalf
fe; f; g; hg: 2
DTBDM consists of two components: decision-tree-based
impulse detector and edge-preserving image filter. The
detector determines whether p
i;j
is a noisy pixel by using
the decision tree and the correlation between pixel p
i;j
and
its neighboring pixels. If the result is positive, edge-
preserving image filter based on direction-oriented filter
generates the reconstructed value. Otherwise, the value will
be kept unchanged. The design concept of the DTBDM is
displayed in Fig. 2.
632 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
Fig. 1. A 3 3 mask centered on p
i;j
.
Fig. 2. The dataflow of DTBDM.
2.1 Decision-Tree-Based Impulse Detector
In order to determine whether p
i;j
is a noisy pixel, the
correlations between p
i;j
and its neighboring pixels are
considered [10], [11], [14], [16], [17], [23], [24], [25], [26], [27],
[28], [29], [30]. Surveying these methods, we can simply
classify them into several waysobserving the degree of
isolation at current pixel [10], [11], [14], [16], [17], [23], [24],
[25], determining whether the current pixel is on a fringe [16],
[17], [26], [27] or comparing the similarity between current
pixel and its neighboring pixels [16], [28], [29], [30]. There-
fore, in our decision-tree-based impulse detector, we design
three modulesisolation module (IM), fringe module (FM),
and similarity module (SM). Three concatenating decisions
of these modules build a decision tree. The decision tree is a
binary tree and can determine the status of p
i;j
by using the
different equations in different modules. First, we use
isolation module to decide whether the pixel value is in a
smooth region. If the result is negative, we conclude that the
current pixel belongs to noisy free. Otherwise, if the result is
positive, it means that the current pixel might be a noisy pixel
or just situated on an edge. The fringe module is used to
confirm the result. If the current pixel is situated on an edge,
the result of fringe module will be negative (noisy free);
otherwise, the result will be positive. If isolation module and
fringe module cannot determine whether current pixel
belongs to noisy free, the similarity module is used to decide
the result. It compares the similarity between current pixel
and its neighboring pixels. If the result is positive, p
i;j
is a
noisy pixel; otherwise, it is noise free. The following sections
describe the three modules in detail.
2.1.1 Isolation Module
The pixel values in a smooth region should be close or locally
slightly varying, as shown in Fig. 3. The differences between
its neighboring pixel values are small. If there are noisy
values, edges, or blocks in this region, the distribution of the
values is different, as shown in Fig. 4. Therefore, we
determine whether current pixel is an isolation point by
observing the smoothness of its surrounding pixels. Fig. 5
shows an example of noisy image. The pixels with shadow
sufferingfromnoise have lowsimilaritywiththe neighboring
pixels and the so-called isolation point. The difference
between it andits neighboring pixel value is large. According
to the above concepts, we first detect the maximum and
minimum luminance values in W
TopHalf
, named as TopHalf_
max, TopHalf_min, andcalculate the difference betweenthem,
named as TopHalf_diff. For W
BottomHalf
, we apply the same
idea to obtain BottomHalf_diff. The two difference values
are comparedwitha thresholdTh IM
a
to decide whether the
surrounding region belongs to a smooth area. The equations
are as
TopHalf diff TopHalf max TopHalf min: 3
BottomHalf diff BottomHalf max BottomHalf min:
4
DecisionI
true; if TopHalf diff Th IM
a

or BottomHalf diff Th IM
a

false; otherwise:
8
<
:
5
Next, we take p
i;j
into consideration. Two values must
be calculated first. One is the difference between f
i;j
and
TopHalf_max; the other is the difference between f
i;j
and
TopHalf_min. After the subtraction, a threshold Th
I
M
b
is
used to compare these two differences. The same method
as in the case of W
BottomHalf
is applied. The equations are as
IM TopHalf

true; if jf
i;j
TopHalf maxj Th IM
b

or jf
i;j
TopHalf minj Th IM
b

false; otherwise:
8
>
<
>
:
6
IM BottomHalf

true; if jf
i;j
BottomHalf maxj Th IM
b

or jf
i;j
BottomHalf minj Th IM
b

false; otherwise:
8
>
<
>
:
7
DecisionII
true; if IM TopHalf true
or IM BottomHalf true
false; otherwise:
8
<
:
8
Finally, we can make a temporary decision whether p
i;j
belongs to a suspected noisy pixel or is noisy free.
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 633
Fig. 3. A smooth region in Lena.
Fig. 4. A nonsmooth region in Lena.
Fig. 5. The difference between noisy and neighboring pixels in Lena.
2.1.2 Fringe Module
If p
i;j
has a great difference with neighboring pixels, it might
be a noisy pixel (discussed in Section 2.1.1 IM) or just
situated on an edge, as shown in Fig. 6. How to conclude
that a pixel is noisy or situated on an edge is difficult. In
order to deal with this case, we define four directions, from
E
1
to E
4
, as shown in Fig. 7. We take direction E
1
for
example. By calculating the absolute difference between f
i;j
and the other two pixel values along the same direction,
respectively, we can determine whether there is an edge or
not. The detailed equations are as
FM E
1

false; if ja f
i;j
j Th FM
a

or jh f
i;j
j Th FM
a

or ja hj Th FM
b

true; otherwise:
8
>
>
<
>
>
:
9
FM E
2

false; if jc f
i;j
j Th FM
a

or jf f
i;j
j Th FM
a

or jc fj Th FM
b

true; otherwise:
8
>
>
<
>
>
:
10
FM E
3

false; if jb f
i;j
j Th FM
a

or jg f
i;j
j Th FM
a

or jb gj Th FM
b

true; otherwise:
8
>
>
<
>
>
:
11
FM E
4

false; if jd f
i;j
j Th FM
a

or je f
i;j
j Th FM
a

or jd ej Th FM
b

true; otherwise:
8
>
>
<
>
>
:
12
Decision III
false; if FM E
1
or FM E
2

or FM E
3
or FM E
4

true; otherwise:
8
<
:
13
2.1.3 Similarity Module
The last module is similarity module. The luminance values
in mask W located in a noisy-free area might be close. The
median is always located in the center of the variational
series, while the impulse is usually located near one of its
ends. Hence, if there are extreme big or small values, that
implies the possibility of noisy signals. According to this
concept, we sort nine values in ascending order and obtain
the fourth, fifth, and sixth values which are close to the
median in mask W. The fourth, fifth, and sixth values are
represented as 4
th
inW
i;j
, MedianInW
i;j
, and 6
th
inW
i;j
. We
define Max
i;j
and Min
i;j
as
Max
i;j
6
th
inW
i;j
Th SM
a
;
Min
i;j
4
th
inW
i;j
Th SM
a
:
14
Max
i;j
and Min
i;j
are used to determine the status of pixel
p
i;j
. However, in order to make the decision more precisely,
we do some modifications as
N
max

Max
i;j
; if Max
i;j
MedianInW
i;j
Th SM
b

MedianInW
i;j
Th SM
b
; otherwise:
8
>
>
<
>
>
:
15
N
min

Min
i;j
; if Min
i;j
MedianInW
i;j
Th SM
b

MedianInW
i;j
Th SM
b
; otherwise:
8
>
>
<
>
>
:
16
Finally, if f
i;j
is not between N
max
and N
min
, we conclude
that p
i;j
is a noise pixel. Edge-preserving image filter will be
used to build the reconstructed value. Otherwise, the
original value f
i;j
will be the output. The equation is as
Decision IV
true; if f
i:j
N
max
or f
i:j
N
min

false; otherwise:

17
Obviously, the threshold affects the quality of denoised
images of the proposed method. A more appropriate
threshold contributes to achieve a better detection result.
However, it is not easy to derive an optimal threshold
through analytic formulation. The fixed values of thresh-
olds make our algorithm simple and suitable for hardware
implementation. According to our extensive experimental
results, the thresholds Th IM
a
, TH IM
b
, Th FM
a
, Th FM
b
,
Th SM
a
, and Th SM
b
are all predefined values and set as
20, 25, 40, 80, 15, and 60, respectively.
2.2 Edge-Preserving Image Filter
To locate the edge existing in the current W, a simple edge-
preserving technique which can be realized easily with VLSI
circuit is adopted. The dataflow and the pseudocode of our
edge-preserving image filter are shown in Figs. 8 and 9,
respectively. Here, we consider eight directional differences,
from D
1
to D
8
, to reconstruct the noisy pixel value, as shown
in Fig. 10 and (18). Only those composed of noise-free pixels
are taken into account to avoid possible misdetection.
Directions passing through the suspected pixels are dis-
carded to reduce misdetection. Therefore, we use Max
i;j
and
Min
i;j
, defined in similarity module, to determine whether
the values of d, e, f, g, and h are likely corrupted,
respectively. If the pixel is likely being corrupted by noise,
we dont consider the direction including the suspected
pixel. In the second block, if d, e, f, g, and h are all suspected
to be noisy pixels, and no edge can be processed, so
^
f
i;j
(the
634 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
Fig. 6. The edge region in Lena.
Fig. 7. Four directions in DTBDM.
estimated value of p
i;j
) is equal to the weighted average of
luminance values of three previously denoised pixels and
calculated as a b 2 c=4. In other conditions, the edge
filter calculates the directional differences of the chosen
directions and locates the smallest one D
min
among themin
the third block. The equations are as follows:
D
1
jd hj ja ej
D
2
ja gj jb hj
D
3
jb gj 2
D
4
jb fj jc gj
D
5
jc dj je fj
D
6
jd ej 2
D
7
ja hj 2
D
8
jc fj 2;
18
^
f
i;j

a d e h=4; if D
min
D
1
;
a b g h=4; if D
min
D
2
;
b g=2; if D
min
D
3
;
b c f g=4; if D
min
D
4
;
c d e f=4; if D
min
D
5
;
d e=2; if D
min
D
6
;
a h=2; if D
min
D
7
;
c f=2; if D
min
D
8
:
8
>
>
>
>
>
>
>
>
>
>
<
>
>
>
>
>
>
>
>
>
>
:
19
In the last block of Fig. 8, the smallest directional difference
implies that it has the strongest spatial relation with p
i;j
, and
probably there exists an edge in its direction. Hence, the
mean of luminance values of the pixels which possess the
smallest directional difference is treated as
^
f
i;j
. After
^
f
i;j
is
determined, a tuning skill is used to filter the bias edge. If
^
f
i;j
obtain the correct edge, it will situate at the median of b,
d, e, and g because of the spatial relation and the
characteristic of edge preserving. Otherwise, the values of

f
i;j
will be replaced by the median of four neighboring
pixels (b, d, e, and g). We can express

f
i;j
as

f
i;j
Median
^
f
i;j
; b; d; e; g: 20
3 VLSI IMPLEMENTATION OF DTBDM
DTBDM has low computational complexity and requires
only two line buffers instead of full images, so its cost of
VLSI implementation is low. For better timing performance,
we adopt the pipelined architecture to produce an output at
every clock cycle. In our implementation, the SRAM used to
store the image luminance values is generated with the
0:18 m TSMC/Artisan memory compiler [31], and each of
them is 512 8 bits. According to the simulation results
obtained from DesignWare of SYNOPSYS [32], we find that
the access time for SRAM is about 5 ns. Hence, we adopt the
7-stage pipelined architecture for DTBDM.
Fig. 11 shows block diagram of the VLSI architecture for
DTBDM. The architecture adopts anadaptive technologyand
consists of five main blocks: line buffer, register bank (RB),
decision-tree-based impulse detector, edge-preserving im-
age filter, and controller. Each of them is described briefly in
the following sections.
3.1 Adaptive Technology
The proposed method employs an adaptive technology to
improve the quality of reconstructedimage. Fig. 11 shows the
architecture of the proposed adaptive algorithm. The
reconstructed pixels are adaptively written or stored into
the line buffers. The current pixel to be denoised is located at
coordinate i; j. The adaptive points located at coordinate
i 1; j 1, i 1; j, and i 1; j 1 are already denoised
at the previous denoising process. Since we adopt a pipelined
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 635
Fig. 8. Dataflow of edge-preserving image filter.
Fig. 9. Pseudocode of edge-preserving image filter.
Fig. 10. Eight directional differences of DTBDM.
hardware architecture in this work, the denoised value
located at coordinate i; j 1 is still in the pipeline and not
available, as shown in Fig. 12. Here, six original points and
three adaptive points are combined as nine input pixels for
the 3 3 maskto reconstruct the resultingpixel

f
i;j
. Although
only three adaptive points (less thanhalf) of nine input points
are available, the reconstructed value is significantly affected
by the adaptive points, since each adaptive point is written
back to influence the next point continuously.
3.2 Line Buffer (Ping-Pong Buffer)
DTBDM adopts a 3 3 mask, so three scanning lines are
needed. If p
i;j
are processed, three pixels from row
i1
, row
i
,
and row
i1
, are needed to perform the denoising process.
Here, we use the concept of ping-pong arrangement. With
the help of four crossover multiplexers (see Fig. 12), we
realize three scanning lines with two line buffers. Odd-Line
Buffer and Even-Line Buffer are designed to store the pixels
at odd and even rows, respectively, as shown in Fig. 12.
To reduce cost and power consumption, the line buffer is
implemented with a dual-port SRAM (one port for reading
out data and the other for writing back data concurrently)
instead of a series of shifter registers. If the size of an image
is I
w
I
h
, the size required for one line buffer is I
w
3 bytes
in which 3 represents the number of pixels stored in the
register bank.
3.3 Register Bank
The register bank, consisting of nine registers, is used to
store the 3 3 pixel values of the current mask W. Fig. 12
shows its architecture where each three registers are
connected serially in a chain to provide three pixel values
of a row in W, and the Reg4 keeps the luminance value f
i;j

of the current pixel to be denoised. Obviously, the

denoising process for p
i;j
doesnt start until f
i1;j1
enterers
from the input device. The nine values stored in RB are then
used simultaneously by subsequent data detector and noise
filter for denoising.
Once the denoising process for p
i;j
is completed, the
reconstructed pixel value

f
i;j
generated by the edge-preser-
ving filter is outputtedandwritten into the line buffer storing
row
i
to replace f
i;j
. When the denoising process shifts from
p
i;j
to p
i;j1
, only three new values f
i1;j2
; f
i;j2
; f
i1;j2
are
needed to be read into RB (Reg2, Reg5, and Reg8, respec-
tively) and other six pixel values are shifted to each ones
proper register. At the same time, the previous input value
from the input device, f
i1;j1
, is written back to the line
buffer storing row
i1
for subsequent denoising process.
The selection signals of the four multiplexers are all set to
1 or 0 for denoising the odd or the even rows, respectively.
Two examples are shown in Fig. 13 to illustrate the
interconnections between the two line buffers and RB.
Assume that we denoise row
2
, and set all four selection
signals to 0, those samples of row
1
and row
2
are stored in
Odd-Line Buffer and Even-Line Buffer, respectively. The
636 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
Fig. 13. Two examples of the interconnections between two line buffers
and RB. Fig. 12. Architecture of register bank in DTBDM.
Fig. 11. Block diagram of VLSI architecture of DTBDM.
samples of row
3
are inputted from the input device, as
shown in Fig. 13a. The previous value in Reg6 and the
denoised results generated by the edge-preserving filter are
written back to Odd-Line Buffer and Even-Line Buffer,
respectively. After the denoising process of row
2
has been
completed, Odd-Line Buffer is now full with the whole
samples of row
3
, while those denoised samples of row
2
are
all stored in Even-Line Buffer. To denoise row
3
, we set all
selections signals to 1. Thus, the previous value in Reg6 and
the denoised results generated by the edge-preserving filter
are written back to Even-Line Buffer and Odd-Line Buffer,
respectively, as shown in Fig. 13b. After the denoising
process of row
3
has been completed, Even-Line Buffer is
now full with the whole samples of row
4
, while those
denoised samples of row
3
are stored in Odd-Line Buffer.
3.4 Decision-Tree-Based Impulse Detector
The decision-tree-based impulse detector is composed of
three modules (isolation module, fringe module, and
similarity module). Each of them is described in the
following sections.
3.4.1 Isolation Module
Fig. 14 shows the architecture of IM (we take W
TopHalf
for
example). The comparator CMP
L
is used to output the
larger value from the two input values while the compara-
tor CMP
S
is used to output the smaller value from the two
input values. The first two-level comparators are used to
find TopHalf_max and TopHalf_min. The SUB unit is used to
output the difference which is subtracted the lower input
(TopHalf_min) from the upper one (TopHalf_max), and the
jSUBj unit is used to output the absolute value of difference
of two inputs. The GC is the greater comparator that will
output logic 1 if the upper input value is greater than the
lower one. The OR gate is employed to generate the binary
result for IM_TopHalf. Finally, if the result of Decision II is
positive, p
i;j
might be a noisy pixel or situate on an edge.
The next module (FM) will be used to confirm the result.
3.4.2 Fringe Module
Fig. 15 shows the architecture of FM. The FM is composed
of four small modules, from FM_1 to FM_4, and each of
them is used to determine its direction, as mentioned in
Section 2.1.2. Fig. 16 is a detailed implementation of FM_1.
Since E
1
is the direction from a to h (Fig. 7), the relation
between a, h, and f
i;j
must be referenced. The three jSUBj
units are used to determine the absolute differences
between them. The GC is described in the above section
and the NOR gate is used to generate the result of FM E
1
. If
the result is positive, we consider that f
i;j
is on the edge E
1
and regard it as noise free.
3.4.3 Similarity Module
If IMand FMcant determine whether f
i;j
belongs to a noise-
free value or not, SM is used to confirm the result. Fig. 17
shows our architecture that is designed to accelerate the
sorting speed to obtain the fourth value in mask W. The
detailed implementation of module M0 is shown in Fig. 18. If
a is greater than b, C01 is set to 1; otherwise, C01 is set to 0.
The eight GC units are used to determine the values from
C01 to C08. After comparing, a combined unit is used to
combine the results of each comparator to obtain a number
between 0 and 8. The number indicates the order of value in
mask W. If a is the smallest value in mask W, the output of
the M0 module is 0; if a is the biggest value in mask W, the
output is 8. The architectures of other modules (M1 to M8)
are almost the same as M0, with only little difference. By
means of this implementation, we can find out the order of
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 637
Fig. 14. Architecture of IM W
TopHalf
.
Fig. 15. Architecture of FM.
Fig. 16. Architecture of FM 1 module.
Fig. 17. Architecture of sorting 4
th
inW.
values efficiently by using simple comparators and com-
bined units. Comparing with traditional sorting algorithms,
this method not only speeds up the sorting time, but also
reduces the space which used to store the value to be
exchanged. Fig. 19 shows the architecture of SM after we
obtain the fourth, fifth, and sixth values in mask W. The SUB
and ADD units are used to calculate the value of Max
i;j
and
Min
i;j
as mentioned in Section 2.1.3. The Two GC and MUX
units are used to determine the N
max
and N
min
. The TCunit is
a triple input comparator which can output the logic 1 if the
lowest input is not between the upper two inputs.
3.5 Edge-Preserving Image Filter
The Edge-Preserving Image Filter is composed of two
modules, minED generator and average generator (AG).
Fig. 20 shows the architecture of the minED generator which
is used to determine the edge that has the smallest
difference. Eight directional differences are calculated with
twelve jSUBj, four ADD, and four shifter units. Then, the
smallest one is determined by using the Min Tree unit. Min
Tree is made up of a series of comparators. After that, the
mean of luminance values of the pixels which process the
smallest directional difference D
min
can be obtained from
the average generator, as shown in Fig. 21. As mentioned in
Section 2, if p
i;j1
; p
i;j1
; p
i1;j1
; p
i1;j
and p
i1;j1
are all
suspected to be noisy pixels, the final MUX will output
a b 2 c=4. Otherwise, the MUX will output the mean
of the pixel values which process D
min
. Some directional
differences are determined according to four pixel values,
so its reconstructive values also need four pixel values.
Two-level ADD and shifter units are used to complete our
calculation. As for the chip implementation, the gate counts
or silicon area of one multiplier or division is much larger
than one shifter. In our design, all multipliers or divisions
will be replaced by shifter units in order to lower the
hardware cost.
After above computations, we sort b, d, e, and g in order.
The reconstructed value
^
f
i;j
obtained from edge-preserving
filter will be compared with the second and third values,
named as SortFour2, SortFour3, and the final value

f
i;j
is
obtained from the equation as
638 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
Fig. 20. Architecture of minED generator.
Fig. 21. Architecture of average generator. Fig. 19. Architecture of SM.
Fig. 18. Architecture of M0 module.

f
i;j

SortFour2; if SortFour2 >
^
f
i;j

SortFour3; if SortFour3 <

^
f
i;j

^
f
i;j
; otherwise:
8
>
<
>
:
21
3.6 Controller
Controller sends signals to control pipelining and timing
statuses of the proposed circuits. It also sends control signals
to schedule reading and writing statuses of the data that are
stored in register bank or in line buffers. The realization of
the controller is based on the concept of finite state machine
(FSM). By the controller design, the proposed circuit can
automatically receive stream-in data of original images and
produce stream-out results of reconstructed images.
4 IMPLEMENTATION RESULTS AND COMPARISONS
To verify the characteristics and the quality of denoised
images of various denoising algorithms, a variety of
simulations are carried out on the six well-known 512 512
8-bit gray-scale test images: Lena, Boat, Couple, Peppers,
Airplane, and Goldhill. For a single test image, the corrupted
versions of it are generated in Matlab environment with
random-valuedimpulse noise at various noise densities from
5 to 20 percent withincrements of 5 percent. Then, we employ
different approaches to detect impulse noise and restore the
corrupted image. Thus, we can easily compare the restored
images withthe source image for various denoising methods.
Totally, 12 denoising methods (Median Filter [8], ACWM
[12], MSM(3:T) [13], MSM(5:T) [13], MSM(7:T) [13], ATMBM
[14], DRID [15], RORD-WMF [16], RVNP [33], AMF [34],
NAVF [35], LCNR [36]) and our method (DTBDM) are
compared in terms of objective testing (quantitative evalua-
tion) and subjective testing (visual quality) where the
parameters or thresholds of these methods are set as
suggested.
We employ the peak signal-to-noise ratio (PSNR) to
illustrate the quantitative quality of the reconstructed
images for various methods. Tables 1, 2, 3, and 4 list the
restoration results in PSNR (dB) of test images corrupted by
5, 10, 15, and 20 percent impulses, respectively. The first 10
belong to lower complexity methods and perform no
iteration. The others belong to higher complexity methods
and have more complicated operations and iterations.
Comparing with those experimental results, the quantita-
tive qualities of DTBDM are always better than those lower
complexity methods in low noise ratio and almost the same
with other higher complexity methods. Table 5 lists the
mask size, line buffer, and iteration times of each methods.
Since most methods are software implementation and some
have complex operations, it is hard to list the detailed
operations, such as the numbers of adder, subtraction,
multiplication, and division. Generally, the cost of VLSI
implementation depends mainly on the required memory
and computational complexity. The proposed design
requires only few computations. Hence, we use line buffer
and iteration times to prove that our design requires lower
cost. In [14], the author claims that their method achieves
better filtering quality with lower complexity than other
methods [9], [10], [11]. Therefore, we can conclude that our
DTBDM outperforms other methods [8], [9], [10], [11], [12],
[13], [14], [15], [16], [33], [34], [35], [36] in terms of
quantitative evaluation.
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 639
TABLE 1
Comparative Results in PSNR (dB) of
Images Corrupted by 5 Percent Impulses
TABLE 2
Comparative Results in PSNR (dB) of
Images Corrupted by 10 Percent Impulses
TABLE 3
Comparative Results in PSNR (dB) of
Images Corrupted by 15 Percent Impulses
Table 6 shows the probabilities of impulse detection,
including the false alarms and misses. The false alarm
means that there is no impulse but detector says there is
one. Since the quantitative qualities of our method are much
better than those lower complexity methods, we only list
the comparisons between our method and other higher
complexity methods. Although ATMBM and DRID can
reduce the numbers of misses by doing iteration, they also
increase the numbers of false alarm, as shown in Table 6.
The total numbers (misses + false alarms) in this work are
much lower than those higher complexity methods.
To explore the visual quality, we show the recon-
structed images of different denoising methods in restor-
ing 20 percent corrupted image Lena and Peppers in
Figs. 22 and 23. Since the quantitative quality of [12], [14],
[15], [16], [36] and our method are better than others, we
take them for visual comparisons only.
The images restored by ACWM, ATMBM, and DRID
have some obvious noise. The reconstructed image of our
method can preserve more details in edges (see stalk of
pepper) as shown in Fig. 22. Clearly, the proposed DTBDM
produces visually pleasing images.
The VLSI architecture of our design was implemented
by using Verilog HDL. We used SYNOPSYS Design Vision
640 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
TABLE 6
Comparisons of the Probabilities of Impulse
Detection for Various Noise Peppers Image
TABLE 5
The Mask Size, Line Buffer, and Iteration Times of Each Method
TABLE 4
Comparative Results in PSNR (dB) of
Images Corrupted by 20 Percent Impulses
Fig. 22. Results of different methods in restoring 20 percent corrupted image Lena.
to synthesize the design with TSMCs 0.18 m cell library.
The layout for the design was generated with SYNOPSYS
Astro (for auto placement and routing), and verified by
MENTOR GRAPHIC Calibre (for DRC and LVS checks).
The synthesis results show that the DTBDM chip contains
21k gate counts. It works with a clock period of 5 ns and
operates at a clock rate of 200 MHz. The power consump-
tion is 17.12 mW with 1.8-V supply voltage. Furthermore,
DTBDM is also implemented on the Altera Stratix II
EP2S60F1020C5 FPGA board for verification. The operating
clock frequency of DTBDM is 163.83 MHz (with 1.29k logic
elements). Since our design requires only simple opera-
tions (fixed bit-width adding, subtracting, or comparing),
the denoised results of DTBDM with software program
and with the VLSI circuit are identical.
To evaluate the circuit, we compared DTBDM with four
recent denoising chips [33], [34], [35], [36]. They were
realized with different VLSI implementations, so it is very
difficult to compare our chip with them directly. Hence, we
have implemented our design by using four different
technologies, respectively. Table 7 shows the detailed
comparisons for various implementations in terms of the
total number of logic elements, line buffer, and frequency.
As demonstrated, DTBDM requires lower hardware cost
and works faster than RVNP [33], AMF [34], and NAVF
[35]. Although the proposed method requires more logic
elements than [36], it can achieve higher frequency and
produce better image quality when denoising an image
corrupted by random-valued impulse noise.
5 CONCLUSIONS
A low-cost VLSI architecture for efficient removal of
random-valued impulse noise is proposed in this paper.
The approach uses the decision-tree-based detector to detect
the noisy pixel and employs an effective design to locate the
edge. With adaptive skill, the quality of the reconstructed
images is notable improved. Our extensive experimental
results demonstrate that the performance of our proposed
technique is better than the previous lower complexity
methods and is comparable to the higher complexity
methods in terms of both quantitative evaluation and visual
quality. The VLSI architecture of our design yields a
processing rate of about 200 MHz by using TSMC 0:18 m
technology. It requires only low computational complexity
and two line memory buffers. Therefore, it is very suitable
to be applied to many real-time applications.
ACKNOWLEDGMENTS
This work was supported in part by the National Science
Council, R.O.C., under Grant NSC-101-2221-E-006-151-MY3
and the Ministry of Economic Affairs (MOEA) of Taiwan,
under Grant number MOEA 100-EC-17-A-05-S1-192. This
research received funding from the Headquarters of
University Advancement at the National Cheng Kung
University, which is sponsored by the Ministry of Educa-
tion, Taiwan, R.O.C.
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 641
Fig. 23. Results of different methods in restoring 20 percent corrupted image Peppers.
TABLE 7
Features of Five Denoising Implementations
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481, Mar. 2010.
Chih-Yuan Lien received the BS and MS
degrees in computer science and information
engineering from National Taiwan University,
Taiwan (R.O.C.), in 1996 and 1998, respec-
tively, and the PhD degree in computer science
and information engineering from National
Cheng Kung University, Taiwan (R.O.C.), in
2009. He is currently an assistant professor in
the Department of Electronic Engineering,
National Kaohsiung University of Applied
Sciences, Taiwan (R.O.C.). His research interests include image
processing, VLSI chip design, and video coding system.
Chien-Chuan Huang received the BS and MS
degree in computer science and information
engineering from National Cheng Kung Univer-
sity, Taiwan (R.O.C.), in 2005 and 2008, respec-
tively. Since September 2008, he has been
working toward the PhD degree in computer
science and information engineering from Na-
tional Cheng Kung University, Taiwan (R.O.C.).
His research interests include image processing,
VLSI chip design, and data compression.
642 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 4, APRIL 2013
Pei-Yin Chen received the BS degree in
electrical engineering from National Cheng Kung
University, Taiwan (R.O.C.), in 1986, the MS
degree in electrical engineering from Penn Sate
University, Pennsylvania, in 1990, and the PhD
degree in electrical engineering from National
Cheng Kung University, Taiwan (R.O.C.), in
1999. He is currently a professor in the Depart-
ment of Computer Science and Information
Engineering, National Cheng Kung University,
Taiwan (R.O.C.). His research interests include VLSI chip design, video
compression, fuzzy logic control, and gray prediction. He is a member of
the IEEE.
Yi-Fan Lin received the BS degree in computer
science from National Sun Yat-sen University,
Taiwan (R.O.C.), in 2006, and the MS degree in
computer science and information engineering
from National Cheng Kung University, Taiwan
(R.O.C.), in 2009. His research interests include
VLSI chip design, data compression, and image
processing.
. For more information on this or any other computing topic,
please visit our Digital Library at www.computer.org/publications/dlib.
LIEN ET AL.: AN EFFICIENT DENOISING ARCHITECTURE FOR REMOVAL OF IMPULSE NOISE IN IMAGES 643