Scribd Logo
Upload

Welcome to Scribd!

  • 297 views

    Divisor de Frecuencia de 50MHz A 1Hz para Parpadeo de LED

    Uploaded by

    epievega
    This document describes a frequency divider circuit that divides a 50MHz clock signal down to 1Hz to blink an LED. It contains the VHDL code for an entity called clk1Hz that defines the input and output ports. The architecture contains processes to divide the frequency and assign signals based on input signals to control the speed and direction of blinking. It also contains physical placement constraints for the inputs and outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Divisor de Frecuencia de 50MHz A 1Hz para Parpadeo de LED

    Uploaded by

    epievega
    297 views2 pages
    This document describes a frequency divider circuit that divides a 50MHz clock signal down to 1Hz to blink an LED. It contains the VHDL code for an entity called clk1Hz that defines the input and output ports. The architecture contains processes to divide the frequency and assign signals based on input signals to control the speed and direction of blinking. It also contains physical placement constraints for the inputs and outputs.

    Original Title

    Divisor de Frecuencia de 50MHz a 1Hz Para Parpadeo de LED

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes a frequency divider circuit that divides a 50MHz clock signal down to 1Hz to blink an LED. It contains the VHDL code for an entity called clk1Hz that defines the input and output ports. The architecture contains processes to divide the frequency and assign signals based on input signals to control the speed and direction of blinking. It also contains physical placement constraints for the inputs and outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    297 views2 pages

    Divisor de Frecuencia de 50MHz A 1Hz para Parpadeo de LED

    Uploaded by

    epievega
    This document describes a frequency divider circuit that divides a 50MHz clock signal down to 1Hz to blink an LED. It contains the VHDL code for an entity called clk1Hz that defines the input and output ports. The architecture contains processes to divide the frequency and assign signals based on input signals to control the speed and direction of blinking. It also contains physical placement constraints for the inputs and outputs.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    --Divisor de frecuencia de 50MHz a 1Hz para parpadeo de LED

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity clk1Hz is
    Port (
    clk50Mhz: in STD_LOGIC;
    reset : in STD_LOGIC;
    giro : in STD_LOGIC;
    half : in STD_LOGIC;
    veloc_in : in STD_LOGIC;
    salida : out STD_LOGIC;
    full : out STD_LOGIC;
    inversion : out STD_LOGIC;
    led : out STD_LOGIC;
    r : out STD_LOGIC
    );
    end clk1Hz;

    architecture Behavioral of clk1Hz is
    signal pulso: STD_LOGIC;
    signal giro_s: STD_LOGIC;
    signal reset_s : STD_LOGIC;
    signal half_s: STD_LOGIC;
    signal velocidad: integer range 0 to 999999 := 0;
    signal contador: integer range 0 to 999999 := 0;--40mhz
    begin
    divisor_frecuencia: process (reset, clk50Mhz) begin
    if (reset = '0') then
    reset_s <= '0';
    pulso <= '0';
    contador <= 0;
    elsif rising_edge(clk50Mhz) then
    reset_s <= '1';
    if (veloc_in = '0') then
    velocidad <= 49999;
    else
    velocidad <= 999999;
    end if;
    if (contador = velocidad) then
    pulso <= NOT(pulso);
    contador <= 0;
    else
    contador <= contador+1;
    end if;
    end if;
    end process;

    process (giro) begin
    if (giro = '0') then
    giro_s <= '0';

    else
    giro_s <= '1';

    end if;
    end process;

    process (half) begin
    if (half = '0') then
    half_s <= '0';

    else
    half_s <= '1';

    end if;
    end process;

    led <= pulso;
    salida <= pulso;
    inversion <=giro_s;
    full <=half_s;
    r <= reset_s;

    end Behavioral;



    # PlanAhead Generated physical constraints

    NET "clk50Mhz" LOC = C9;
    NET "full" LOC = D5;
    NET "giro" LOC = H18;
    NET "half" LOC = L14;
    NET "inversion" LOC = B4;
    NET "led" LOC = F12;
    NET "reset" LOC = L13;
    NET "salida" LOC = A4;
    NET "r" LOC = C5;
    NET "veloc_in" LOC = N17;

    You might also like