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Experiment 1: Aim: WAP in VHDL To Implement Basic Gates

The document describes experiments in VHDL to implement basic logic gates, a half adder, and a full adder. It includes the source code for entities defining each gate or circuit using ports and architectures with logic expressions to compute the outputs from the inputs. AND, OR, NOR, NOT, XNOR, XOR, NAND gates and a half adder and full adder are implemented. The output is not shown for any of the experiments.

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Mrigya Jain
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45 views10 pages

Experiment 1: Aim: WAP in VHDL To Implement Basic Gates

The document describes experiments in VHDL to implement basic logic gates, a half adder, and a full adder. It includes the source code for entities defining each gate or circuit using ports and architectures with logic expressions to compute the outputs from the inputs. AND, OR, NOR, NOT, XNOR, XOR, NAND gates and a half adder and full adder are implemented. The output is not shown for any of the experiments.

Uploaded by

Mrigya Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 1

Aim : WAP in VHDL to Implement basic gates



AND Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity and1 is
port(x,y: in std_logic; z: out std_logic);
end and1;
architecture data_and1 of and1 is
begin
z <= x and y;
end data_and1;


Output :




OR Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity or1 is
port(x,y: in std_logic; z: out std_logic);
end or1;
architecture data_or1 of or1 is
begin
z <= x or y;
end data_or1;


Output :







NOR Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity nor1 is
port(x,y: in std_logic; z: out std_logic);
end nor1;
architecture data_nor1 of nor1 is
begin
z <= x nor y;
end data_nor1;


Output :







NOT Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity not1 is
port(x: in std_logic; z: out std_logic);
end not1;
architecture data_not1 of not1 is
begin
z <= not x;
end data_not1;


Output :








XNOR Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity xnor1 is
port(x,y: in std_logic; z: out std_logic);
end xnor1;
architecture data_xnor1 of xnor1 is
begin
z <= x xnor y;
end data_xnor1;


Output :








XOR Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port(x,y: in std_logic; z: out std_logic);
end xor1;
architecture data_xor1 of xor1 is
begin
z <= x xor y;
end data_xor1;


Output :








NAND Gate:
Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity nand1 is
port(x,y: in std_logic; z: out std_logic);
end nand1;
architecture data_nand1 of nand1 is
begin
z <= x nand y;
end data_nand1;


Output :








Experiment 2
Aim : WAP in VHDL to Implement Half Adder

Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity hf1 is
port(x,y: in std_logic; sum,carry: out std_logic);
end hf1;
architecture data_hf1 of hf1 is
begin
sum <= x xor y;
carry <= x and y;
end data_hf1;


Output :





Experiment 3
Aim : WAP in VHDL to Implement Full Adder

Source Code:
library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port(x,y,z: in std_logic; sum,carry: out std_logic);
end fa1;
architecture data_fa1 of fa1 is
begin
sum <= x xor y xor z;
carry <= (x and y) or (y and z) or (x and z);
end data_fa1;


Output :

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