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Tutorial 3: Insert Scan Chain Using Design Compiler Authors: Bibhas Ghoshal & Subhadip Kundu

The document provides a tutorial on how to insert a scan chain into a design using Design Compiler. It outlines 11 steps: 1) create a project folder, 2) invoke the DftCompiler, 3) read the input netlist, 4) perform scan-ready synthesis, 5) configure the ATE signals, 6) perform pre-scan checks, 7) specify the scan chain configuration, 8) preview the scan specification, 9) synthesize the scan chain, 10) save the scan-inserted netlist, and 11) report the area of the scan-inserted netlist. The overall goal is to insert a scan chain and compare the area impact.

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370 views

Tutorial 3: Insert Scan Chain Using Design Compiler Authors: Bibhas Ghoshal & Subhadip Kundu

The document provides a tutorial on how to insert a scan chain into a design using Design Compiler. It outlines 11 steps: 1) create a project folder, 2) invoke the DftCompiler, 3) read the input netlist, 4) perform scan-ready synthesis, 5) configure the ATE signals, 6) perform pre-scan checks, 7) specify the scan chain configuration, 8) preview the scan specification, 9) synthesize the scan chain, 10) save the scan-inserted netlist, and 11) report the area of the scan-inserted netlist. The overall goal is to insert a scan chain and compare the area impact.

Uploaded by

kamlesh2589
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Tutorial 3 : Insert Scan Chain using Design Compiler

Authors: Bibhas Ghoshal & Subhadip Kundu


Objectives:
1. How to insert scan chain into a design .
2. Compare the area of synthesized netlist and scan inserted netlist.

1. Create a folder named dft in the project folder s27


>> mkdir dft
2. Invoke DftCompiler
Dft Compiler is actually embedded in the Design Compiler thus to invoke Dft
Compiler, invoke design_vision
>> design_vision (GUI mode)
3.Read Input Netlist
Read the synthesized netlist s27_syn.v created in Tutorial 2(b) from the syn folder of your project
directory.
File-> Read (read s27_syn.v)
On reading the netlist, check whether the top level design is s27. If not then you can do either of the
following:
i. current_design 27 at the command prompt of design_vision window
The screenshots below show the current design after the netlist is read and after current_deisgn
command is typed.

ii. Open the s27_syn.v in a text editor. Cut the verilog module s27 (at the end of the file ) and paste it
at the top of the file. Save the file and exit the editor.
Read the netlist again. This time you can see s27 as the top level module.

4. Scan Ready Synthesis :


Although you have done the synthesis before, you did not use the scan option.
This compilation (with scan option) considers the impact of scan insertion on mission mode
constraints during optimization. This scan option causes the command to replace all sequential
elements during optimization. Type these lines.
----------------------------------------------------------------set_scan_configuration style multiplexed_flip_flop
compile scan
----------------------------------------------------------------5. ATE configuration
To create a test clock waveform, type
-----------------------------------------------------------------------------------------------set_dft_signal -view existing_dft -type ScanClock -port CK -timing [list 40 60]
-----------------------------------------------------------------------------------------------To create a test default ports, type
---------------------------------------create_test_protocol
---------------------------------------6. Pre-scan Check
This command checks if your follow the gate-level scan design rule. Type
----------------------------------------dft_drc
-----------------------------------------

7. Scan specification
This step tells the Dft Compiler how many scan chains you want. You can also specify the names
of scan related pins (scan_enable, scan_in, scan_out). We will let Dft Compiler to choose the pin
names for us.
-----------------------------------------------set_scan_configuration -chain_count 1
-----------------------------------------------8.Scan preview
This step checks your scan specification for consistency.
-------------------------preview_dft
-------------------------9. Scan chain synthesis : stitch your scan cells into a chain.
-----------------------------insert_dft
-----------------------------You should get the schematic view as shown in following screenshot.

10. Save your scan inserted netlist in the folder dft


------------------------------------------------------------write -format verilog -hierarchy -output s27_dft.v
-------------------------------------------------------------11. Report Area of your scan inserted netlist

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