Tutorial on Trimodal Programming

on z/OS
SHARE 118 in Atlanta, Session 10409
Avri J. Adleman, IBM
[email protected]
(Presented by John Ehrman, IBM)
March 16, 2012
AJA-2
Historical perspective Historical perspective

Classical S360/370

(1964) Only 24-bit addressing supported

370/XA

(1981) Bimodal addressing: 24- or 31-bit addressing

ESA/390
(1988) Dataspaces and Access Registers
z/Architecture
(2001) Trimodal addressing: 24-, 31-, or 64-bit
addressing
AJA-3
Memory layout Memory layout
Below the 16M Line
24 Bit Addressing
Code: RMODE=24
Data: GETMAIN LOC=BELOW
Above the 16M Line
31 Bit Address
Code: RMODE=ANY

(may be below the line)
Data: GETMAIN LOC=ANY

(may be below the line)
Above the 2G Bar
64 Bit Address
Code: None (as yet)
Data: IARV64
0
16 Megabytes
(2
24
Bytes)
2 Gigabytes
(2
31
Bytes)
16 Exabytes
(2
64
Bytes)
Blackout Area (2G)
Below the 16M
Line
Data & Code
Above the 16M
Line
Data & Code
Above the 2G Bar
Data Only
System
Code and/or Data
AJA-4
Terminology: all machine generations Terminology: all machine generations
Byte 8 bits
Halfword 2 Bytes (16 Bits)
Fullword (Word) 4 Bytes (32 Bits)
Doubleword 8 Bytes (64 Bits)
Quadword 16 Bytes (128 Bits)
Notation: 64-bit based [32-bit based]
64-bit based (Doubleword)
32-bit based (Fullword)
Positions:
High Order refers to the low numbered bits
Low Order refers to the high numbered bits
AJA-5
Registers Registers
16 General Purpose Registers
In all generations of processors
Pre-z/Architecture
32 bits in size (the Traditional environment)
z/Architecture
64 bits in size: (sometimes called Grande)
Low Order Word: same as with Pre-z/Architecture processors
TraditionalInstructions that use 24- and 31-bit addressing
High Order Word: z/Architecture Extension
New z/Architecture Instructions
Modal and modeless
64 bit addressing
Ignored by traditionalmodeless instructions
AJA-6
Address formats Address formats
24-bit addressing
31-bit addressing

64-bit addressing
8 Bits 24 bits
0,1 . . . 7,8 . . . 31
1
Bit 31 Bits
0 1 . . . 31
(32 Bits High Half: New) 64 Bits (32 Bits Low Half: Old)
0 . . . 31, 32 . . . 63
AJA-7
24-bit addressing in System/360 24-bit addressing in System/360

General Purpose Registers

32 bits
High 8 bits (0 to 7) for user (flags, etc)
BALR instruction (ILC, CC, Program Mask)
DCB fields
Low 24 bits (8 to 31) for addressing
Special addressing-mode instructions
None (none needed!)
AJA-8
24- and 31-bit addressing in 370/XA 24- and 31-bit addressing in 370/XA

General Purpose Registers

32 Bits
High Order bit indicates addressing mode
0 for 24-bit addressing, 1 for 31-bit addressing
Bits 1 to 7 depend on addressing mode
Part of the address (31-bit addressing)
Flags, etc. (24-bit addressing)
Special addressing-mode instructions
BSM (Branch and Set Mode)
BASSM (Branch and Save and Set Mode)
More about these two, later
AJA-9
64-, 31-, and 24-bit addressing in 64-, 31-, and 24-bit addressing in
z/Architecture z/Architecture
General Purpose Registers: 64 Bits (Doubleword)
32 Bit Extension (High Order Word)
Part of Address, Data, or Unused
32 Bit Original (Low Order Word)
Retains Addressing Methodology for 24 -and 31-bit processing
Low order Bit 63[31]
Considered part of address -or- 64-bit addressing-mode indicator!
Special addressing-mode instructions
Traditional:
BASSM, BSM
New with z/Architecture:
SAM24, SAM31, SAM64 and TAM
AJA-10
PSW description: 2 architecture modes PSW description: 2 architecture modes
ESA/390 mode
Doubleword (64 Bits )
Bit 12 is always 1
Bit 31 is always 0
Instruction Address:
Bits 33 to 63
Addressing Mode (A)
Bit 32 determines addressing
mode
0 in 24-bit mode
1 in 31-bit mode
z/Architecture mode
Quadword (128 Bits)
Bit 12 is always 0
Bit 31 contains the EA mode
Instruction Address
Bits 64 to 127
Addressing mode
Bit 31 (EA): Extended Addressing
Mode
Bit 32 (BA): Basic Addressing
Mode
EA(0) EA(1)
BA(0) 24 Invalid
BA(1) 31 64
Addressing Modes
AJA-11
PSW formats: 2 architecture modes PSW formats: 2 architecture modes
ESA/390: Doubleword (64 bits)
Instruction Address (Bits 0 to 31)
Instruction Address (Bits 32 to 63)
z/Architecture: Quadword (128 bits)
Instruction Address A
0 R 000 T I E Key 1 M W P AS CC Mask 0000 0000
0 R 000 T I E Key 0 M W P AS CC Mask 0000 000
Zero-Filled (Bits 33 to 63)
B
E
AJA-12
Architecture-mode-dependent Architecture-mode-dependent
instructions instructions
Processed differently based on Architecture Mode:
Same code may behave differently in z/Architecture mode vs.
non- z/Architecture (ESA/390) mode
Small (rare) number of cases
Examples:
BAKR and PR
Saves/Restores 64 bit registers
ESTA
PSW functions
BASSM & BSM
We will talk more about these two
Differences are minimal
They do what you would expect
AJA-13
Modeless instructions Modeless instructions
Independent of architecture mode and addressing mode
Function is identical
Generally non-storage access type instructions
Register-register type instructions
Size of register access implied by instruction name
General Purpose Registers
Pre-z/Architecture instructions
Operate only on low order word (bit 32[0] to bit 63[31])
High order word (bits 0 to 31 of 64) ignored
Examples: L, LR, A, AR, M, MR, SRDA,
z/Architecture instructions
Operate either on 32-bit or all 64-bit registers
Examples: LGR (64-64), AGFR (64-32), RLL (32), RLLG (64),
AJA-14
" Regular" " Regular" modal instructions (1) modal instructions (1)
Addresses function differently based on addressing mode
Base and Displacement are no different
May be hybrid with modeless
Very predictable
No hidden surprises
Generally the most commonly used instructions
Examples:
MVC both storage operands depend on addressing mode
Loads and Stores (hybrids)
Arg
1
(register) size is based on instruction name (e.g. L vs LG)
Arg
2
(base and displacement) depends on addressing mode
AJA-15
" Regular" " Regular" modal instructions (2) modal instructions (2)
Load Address Types
LA, LAE, LAY: R
1
,D
2
(X
2
,B
2
)
Modal Processing 64-bit register
24-bit (high word is unchanged)
Low order word
Clears eight bits: 32[0] to 39[7]
Retains all other bits
31-bit (high word is unchanged)
Low order word
Clears one bit: 32[0]
Retains all other bits
64-bit
Sets full 64 bit register
Lengths in registers usually interpreted based on addressing modes
Examples: CLCLE, MVCLE, TRE, etc.
Some do not, such as MVCL and CLCL
FF FF FF FF 00 FF FF FF
FF FF FF FF 7F FF FF FF
FF FF FF FF FF FF FF FF
AJA-16
" Irregular" " Irregular" modal instructions modal instructions
Function differently based on addressing mode
Reference or address storage
Base and Displacement
Register storage reference
Have possible unpredictable side effects or processing
Visit: Principles of Operations
Read the fine print!
Not many cases; usually, extensive or complex instructions
Examples:
TRT sets GPR 1 differently depending on addressing mode
ESTA (see code 1)
If possible use code 4
AJA-17
Mode-switching instructions Mode-switching instructions
Branch & Set Mode
BSM R
1
,R
2
RR-Format:
R
1
= 32- or 64-bit register
R
1
0
Receives PSW addressing
mode bit only; rest unchanged
R
1
= 0
No Address mode bit saved
R
2
= 32- or 64-bit register
R
2
0
Branch-to address
New addressing mode
R
2
= 0
No Branching
No Address Mode bit saved
Branch & Save & Set Mode
BASSM R
1
,R
2
RR-Format:
R
1
= 32- or 64-bit register
R
1
any register number
Receives current PSW
address (of next instruction)
and PSW addressing mode
R
2
= 32- or 64-bit register
R
2
0
Branch-to address
New addressing mode
R
2
= 0
No Branching
No Address Mode bit saved
0B R
1
R
2
0C R
1
R
2
AJA-18
Register addressing-mode formats for Register addressing-mode formats for
BSM and BASSM BSM and BASSM
Bits: 0 to 31 32 33 to 39 40 to 62 63
Ignored 0 Ignored Address 0

Ignored 1 Address 0

Address 1

Bit Mappings
24-Bit Addressing Mode
31-Bit Addressing Mode
64-Bit Addressing Mode
Mode Setting Bit
AJA-19
BASSM & BSM addressing BASSM & BSM addressing
Pre z/Architecture
Always an even branch
address
32-bit Register Only
High order bit mode setting
0 for 24-bit addressing
1 for 31-bit addressing
Low order bit
Part of instruction address
0: Valid
1: Odd instruction
address; Invalid!
z/Architecture 64-bit
Always an even branch
address
64-bit register
Low-order bit (63)
Not used as part of branch
address
0 for 24-, 31-bit addressing
1 for 64-bit addressing
High/Low order bit 32[0]
For 24-, 31-bit addressing
determines mode as in pre-
z/Architecture
For 64-bit mode, part of
instruction address
Note !!!
AJA-20
Mode-switching examples: Mode-switching examples:
calls within a single assembly calls within a single assembly
* Goto 24-bit mode from any mode
LA R15,GOTO24
BASSM R14,R15
* Goto 31-bit mode from any mode (1)
L R15,GOTO31@
BASSM R14,R15
* Goto 31-bit mode from any mode (2)
LARL R15,GOTO31
OILH R15,X'8000'
BASSM R14,R15
* Goto 64-bit mode from any mode
XGR R15,R15 For 24/31->64
LARL R15,GOTO64
OILL R15,X'0001'
BASSM R14,R15
GOTO31@ DC A(GOTO31+X'80000000')
* Entry into 24-bit Mode
GOTO24 DC 0H Below the line
. . .
BSM 0,R14 Return to Caller
* Entry into 31-bit Mode
GOTO31 DC 0H Below/Above line
. . .
BSM 0,R14 Return to Caller
* Entry into 64-bit Mode
GOTO64 DC 0H Below/Above line
. . .
BSM 0,R14 Return to Caller

AJA-21
z/Architecture addressing-mode z/Architecture addressing-mode
instructions instructions
SAMxx:
Set Addressing Mode
E-Type (2-Byte) format with Opcode X'010x'
No registers set/modified; no register preload required
Old mode not retained
Types
SAM24: Switch to 24 bit addressing mode
SAM31: Switch to 31 bit addressing mode
SAM64: Switch to 64 bit addressing mode
TAM
Test Addressing Mode
E-Type (2-byte) format:
Sets condition code based on current addressing mode
CC=0 24-bit addressing (Branch on Zero)
CC=1 31-bit addressing (Branch on Mixed)
CC=2 Unused
CC=3 64-bit addressing (Branch on One)
No registers set or changed
Addressing mode is not switched
01 0B
01 0C
01 0D
01 0E
* Examples:
SAM24 , To AMODE(24)
. . .
SAM31 , To AMODE(31)
. . .
SAM64 , To AMODE(64)
. . .
TAM , Test AMODE
JZ IN24
JO IN64
* Running in AMODE(31)
IN31 DS 0H
. . .
* Running in AMODE(31)
IN24 DS 0H
. . .
* Running in AMODE(64)
IN64 DS 0H
. . .
AJA-22
BALR vs. BASR BALR vs. BASR
BALR R
1
,R
2
Since S/360
High order word
24-, 31-bit mode: ignored
64-bit mode: part of address
Processing Modes (R
1
)
24-bit addressing contains ILC,
CC, Program Mask, 24 bit
address
31- and 64-bit addressing,
identical to BASR
Deprecated now
Use BASR for branch and link
Use IPM instruction for CC
and Program Mask
BASR R
1
,R
2
Since XA/370 (bimodal)
High order word
24-, 31-bit mode: ignored
64-bit mode: part of address
Processing Modes (R
1
)
24- and 31-bit addressing:
contains mode bit and address
64-bit addressing: contains
only the address, no mode
bit(s)
Preferred method of branch and
link (or save) without mode
switching
More consistent
AJA-23
Memory referencing by 64-bit addresses Memory referencing by 64-bit addresses
Blackout Area (2G)
Below the 16M
Line
Data & Code
Above the 16M
Line
Data & Code
Above the 2G Bar
Data Only
System
Code and/or Data
XX XX XX XX ?? ?? ?? ??
00 00 00 00 8? ?? ?? ??
00 00 00 00 0X ?? ?? ??
00 00 00 00 00 ?? ?? ??
XX
At least one bit is not
zero among all XXs
??
Any bit combination
8?
High-order bit is one, all
others any combination
0X
High-order bit is zero,
seven other bits any
combination with at least
one bit set to one.
00
All bits zero
Legend
AJA-24
Special considerations Special considerations
16M Line
System data and code straddles the line
Application code or data will not cross over
GETMAIN either totally below or above the line
Program object segment (class) will either be totally below or above the
line
2G Bar
Blackout zone for MVS is first 2G above the 2G bar
Technically, a valid addressable region!!
Applies to a 64-bit address
High word is all zeroes
Low Order word has address with bit (32[0]) set to 1
IARV64 will not allocate storage in blackout zone
AJA-25
The useful LLGT and LLGTR The useful LLGT and LLGTR
instructions instructions
Load Logical Grande Thirty One Bits
LLGT R
1
,D
2
(X
2
,B
2
)
RXY Format:
LLGTR R
1
,R
2
RRE Format:
Source (Register or Storage)
Fullword, 32 bits (Arg
2
)
Target Register (R
1
)
Doubleword, 64 bits
High word set to all zeroes
Low order word copied from source
Low order word, High Bit 32[0] set to 0
E3 R
1
X
2
B
2
DL
2
DH
2
17
B9 17 ?? R
1
R
2
FF FF FF FF
7F FF FF FF 00 00 00 00
AJA-26
Example: Call and Return Example: Call and Return
TITLE BAD CASE
MYPGM CSECT ,
MYPGM AMODE MY_AMODE
MYPGM RMODE MY_RMODE
AMODE EQU ... bit setting ...
. . .
L R15,YOURPGM@
BASR R14,R15
. . .
YOURPGM@ DC A(YOURPGM+AMODE)
END ,
YOURPGM CSECT ,
YOURPGM AMODE YOUR_AMODE
YOURPGM RMODE YOUR_RMODE
. . .
BSM 0,R14
END ,
TITLE GOOD CASE
MYPGM CSECT ,
MYPGM AMODE MY_AMODE
MYPGM RMODE MY_RMODE
AMODE EQU ... bit setting ...
. . .
XGR R15,R15 <--Important!
L R15,YOURPGM@
BASSM R14,R15
. . .
YOURPGM@ DC A(YOURPGM+AMODE)
END ,
YOURPGM CSECT ,
YOURPGM AMODE YOUR_AMODE
YOURPGM RMODE YOUR_RMODE
. . .
BSM 0,R14
END ,
BAD CASE: Worked OK for MY_AMODE=YOUR_AMODE for 24 and 31 but fails for 64
Fails for MY_AMODEYOUR_AMODE
GOOD CASE: Works for all MY_AMODE and YOUR_AMODE values
AJA-27
Notes: Call and Return Notes: Call and Return

Make sure CALL and RETURN types match

BASSM with BSM

BASR with BR

Be sure alternatives are valid

LINK vs. LOAD and CALL

LINK: switches address mode as required
LOAD and CALL: does not switch addressing mode
Watch out for addressing-mode bits as part of address
May have to clear address mode in register
Especially odd address and AMODE 64
AJA-28
Example: The KILLER bit! Example: The KILLER bit!
TITLE BAD PROGRAM
MYPGM CSECT ,
MYPGM AMODE 31
MYPGM RMODE ANY
STM R14,R12,12(R13)
BASR R11,0
USING *,R11
. . .
SAM64 ,
******************************************
* The Next Instruction Abends!!! *
* (because BASR executed in AMODE(31)) *
******************************************
MVC DATA1,DATA2
. . .
DATA1 DS CL10
DATA2 DC CL10TESTING
. . .
END ,
TITLE GOOD PROGRAM
MYPGM CSECT ,
MYPGM AMODE 31
MYPGM RMODE ANY
STM R14,R12,12(R13)
BASR R11,0
USING *,R11
. . .
SAM64 ,
******************************************
* The Next Instruction Saves the Day *
* (Removes Blackout Area Addressing) *
******************************************
LLGTR R11,R11
MVC DATA1,DATA2
. . .
DATA1 DS CL10
DATA2 DC CL10TESTING
. . .
END ,

AJA-29
Linkage considerations Linkage considerations
New Instructions
Save and Load 64 bit registers
STMH, LMH, STG, LG, STMG, LMG, LMD
More on this follows
Save Areas
Traditional 72 byte save area
32-bit registers
Standard Linkage
New Save Area Layout
64-bit registers
Standard linkage
Transitional
AJA-30
Store/Load (Multiple) high halves of Store/Load (Multiple) high halves of
registers registers

Store/Load High Half of Grande Registers

Only high words 32 bits saved

Format RSY (extended displacement)

STMH R
1
,R
3
,D
2
(B
2
)
LMH R
1
,R
3
,D
2
(B
2
) )

Analogous to STM and LM

Acts on range of registers

No Store or Load instructions for high half of a single
register
Use multiple-type instruction with R
1
= R
3
EB R
1
R
3
B
2
DL
2
DH
2
26
EB R
1
R
3
B
2
DL
2
DH
2
96
AJA-31
Store/Load entire 64-bit registers Store/Load entire 64-bit registers
STG and LG
Store and Load single 64-bit register
Analogous to ST (STY) and L (LY)
Format RXY:
STG R
1
,D
2
(X
2
,B
2
)
LG R
1
,D
2
(X
2
,B
2
)
STMG and LMG
Store and Load multiple 64-bit registers
Analogous to STM (STMY) and LM (LMY)
Format RSY:
STMG R
1
,R
3
,D
2
(B
2
)
LMG R
1
,R
3
,D
2
(B
2
)
E3 R
1
X
2
B
2
DL
2
DH
2
24
E3 R
1
X
2
B
2
DL
2
DH
2
04
EB R
1
R
3
B
2
DL
2
DH
2
04
EB R
1
R
3
B
2
DL
2
DH
2
24
AJA-32
Load Multiple Disjoint Load Multiple Disjoint
LMD R
1
,R
3
,D
2
(B
2
),D
4
(B
4
)
Format SS:
Loads range of full 64-bit registers
Uses two different locations
High half registers loaded from Arg
2
Low half registers loaded from Arg
4
Equivalent to doing a LMH and LM in one instruction!
Allows AMODE=64 code to load saved Grande registers from
two different save areas (high and low words)
Prevents register corruption on needed addresses
Notes:
For performance, use sparingly:
Use LMH and LM or LMG if possible
There is no Store Multiple Disjoint
EF R
1
R
3
B
2
D
2
B
4
D
4

* Example of LMD
STMH R2,R5,HIREGS
STM R2,R5,LOWREGS
. . .
LMD R2,R5,HIREGS,LOWREGS
. . .
HIREGS DS 4F Save High Half
LOWREGS DS 4F Save Low Half
AJA-33
Save areas: old and new Save areas: old and new
IHASAVER macro in SYS1.MACLIB
Types of save areas:
Traditional 72 byte save area
32-bit register save
Standard Linkage
Format 4
64-bit register save
Standard linkage
Eye catcher F4SA at offset X'04'
Relocates previous and next chains to offset 128 (dec) and 136 (dec)
Format 5
64-bit register save like format 4
32-bit high register save area appended
Used for transition from 32 to 64 bit register processing
Standard linkage (like format 4)
Eye catcher F5SA at offset X'04'
Relocates previous and next chains to offset 128 (dec) and 136 (dec)
AJA-34
Save area layouts Save area layouts
Traditional z/Architecture 64-Bit
+00 Reserved for Languages
+04 Previous Chain Pointer
+08 Next Chain Pointer
+0C Return Address (R14)
+10 Entry Address (R15)
+14 GPR R0 to R12 Saved
+00 Reserved for Languages
+04 F4SA or F5SA
+08 Return Address (G14)
+10 Entry Address (G15)
+18 GPR G0 to G12 Saved
+80 Previous Chain Pointer
+88 Next Chain Pointer
F5SA Extension
+90 High Half Save of
GPR G0 to G15
Upper Half of Registers to New Save
Area
Lower Half of Registers to Old Save
Area
AJA-35
Sample program Sample program
Two routines
Sample1
Runs either in 24- or 31-bit mode
Performs I/O to read and write records
Driver for a 64-bit-mode processing routine
RTN64
Entered in callers mode (24 or 31)
Uses F5SA save area to save registers
Processes records in 64-bit mode
Allocates and deletes storage above the 2G bar
IARV64
Accesses storage above the 2G bar
Uses 64 bit registers
PRINT NOGEN
SAMPLE1 CSECT ,
SAMPLE1 AMODE 31
SAMPLE1 RMODE 24
***********************************************************************
* PROGRAM SAMPLE1 - SAMPLE CALLING 64 BIT PROCESS ROUTINE FROM *
* 24/31 BIT PROGRAM *
* *
* PROCESS IS NOT RENT *
*=====================================================================*
* PROGRAM WRITTEN BY: ARI !" ADLEMAN *
* ADLEMAN#US"IBM"COM *
* $%32& 4'4-6('3 *
*=====================================================================*
* PROCESS: SAMPLE1 READS IN AN )( BYTE RECORD DATASET AND CALLS *
* T*E RTN64 TO STORE T*E RECORDS ABOE T*E 2G BAR" *
* *
* AFTER ALL T*E RECORDS ARE READ INTO RTN64 AREA, T*E *
* RECORDS ARE T*EN SORTED" *
* *
* SAMPLE1 T*EN RETRIEES T*E RECORDS, ONE AT A TIME AND *
* OUTPUTS T*E IMAGE" *
* *
* PROGRAM SAMPLE1 PERFORMS ALL I/O FUNCTIONS AND ACTS AS *
* A DRIER TO T*E RTN64 ROUTINE" T*E RTN64 ROUTINE PERFORMS *
* A ARIETY OF PROCESSES ON T*E ABOE T*E 2G BAR STORAGE *
* ARRAY" T*EY INCLUDE: *
* $1& INITIALI+E T*E ABOE T*E BAR REGION *
* $2& TERMINATES $DELETES& T*E ABOE T*E BAR REGION *
* $3& STORES RECORDS, ONE AT A TIME, SE,UENTIALLY *
* $4& SORTS T*E RECORDS *
* $-& RETURNS T*E CURRENT RECORD COUNT *
* $6& RETURNS ONE RECORD AT A TIME BY INDE. *
*=====================================================================*
* 32-BIT REGISTER DEFINITIONS *
***********************************************************************
R( E,U ( ----
R1 E,U 1 PARMLIST
R2 E,U 2 WOR/ REG
R3 E,U 3 WOR/ REG
R4 E,U 4 ----
R- E,U - ----
R6 E,U 6 ----
R% E,U % ----
R) E,U ) ----
R' E,U ' ----
R1( E,U 1( ----
R11 E,U 11 PROGRAM BASE
R12 E,U 12 ----
R13 E,U 13 SAE AREA ADDRESS
R14 E,U 14 RETURN ADDRESS
R1- E,U 1- ENTRY/RETURN CODE
***********************************************************************
* SETUP STANDARD LIN/AGE IN MAINLINE *
***********************************************************************
SAE $14,12&,,SAMPLE1-64-BIT-E.AMPLE-0SYSDATC-0SYSTIME
BASR R11,( SET R11 - PROGRAM BASE
USING $*,ENDMAIN&,R11 SETUP BASE
ST R13,SAE14 BAC/WARD C*AIN
LA R),SAE R) -2 NEW SAE AREA
ST R),)$,R13& FORWARD C*AIN
LR R13,R) R13 : CURRENT SAE AREA
OPEN $INDCB,$INPUT&,OUTDCB,$OUTPUT&&,MODE=31
LA R1,INITPARM R1 -2 INITIALI+E PARM
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
***********************************************************************
* OERALL INPUT RECORDS STORE INTO ABOE T*E BAR ARRAY *
***********************************************************************
READLOOP DS (*
GET INDCB GET A RECORD
ST R1,ADDREC# SAE T*E RECORD ADDRESS
LA R1,ADDPARM R1 -2 ADD RECORD PARMS
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
! READLOOP GET NE.T RECORD
***********************************************************************
* *IT T*E END OF FILE - START PROCESSING *
***********************************************************************
EOF DS (*
***********************************************************************
* SORT T*E RECORDS *
***********************************************************************
LA R1,SORTPARM R1 -2 INITIALI+E PARM
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
***********************************************************************
* GET T*E RECORD COUNT *
***********************************************************************
LA R1,COUNTPRM R1 -2 INITIALI+E PARM
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
***********************************************************************
* PUT OUT *EADER WIT* RECORD COUNT *
***********************************************************************
L R-,COUNTNUM R- = RECORD COUNT
CD R-,DWD MA/E DECIMAL IMAGE
UNP/ *EADNUM,DWD MA/E PICTURE
M+ *EADNUM1L3*EADNUM-1$1&,*EADNUM
PUT OUTDCB,*EADER PUT *EADER TO OUTPUT
***********************************************************************
* RETRIEE AND PRINT ALL RECORDS *
***********************************************************************
.R R3,R3 R3 = RECORD NUMBER
L*I R4,1 R4 = INCREMENT
A*I R-,-1 DECREMENT COUNT
!M DONE IF COUNT 4= (, DONE
RETRLOOP DS (*
ST R3,RETRNUM SAE NUMBER
CD R3,DWD MA/E
UNP/ DATANUM,DWD MA/E PICTURE
M+ DATANUM1L3DATANUM-1$1&,DATANUM
CD R3,DWD DWD = PICTURE OF COUNT
LA R1,RETRPRM R1 -2 RETRIEE PARM LIST
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
PUT OUTDCB,DATA PUT RECORD TO OUTPUT
!.LE R3,R4,RETRLOOP CONTINUE OER ALL RECORDS
***********************************************************************
* REMOE T*E ARRAY *
***********************************************************************
DONE DS (*
LA R1,TERMPARM R1 -2 TERMINATION PARM
LARL R1-,RTN64 R1- -2 64 BIT PROCESSOR
BASR R14,R1- CALL ROUTINE
CLOSE $INDCB,,OUTDCB&,MODE=31
FREEPOOL INDCB
FREEPOOL OUTDCB
L R13,4$,R13& R13 -2 OLD SAE
L R14,12$,R13& R14 = RETURN ADDRESS
.R R1-,R1- R1- = ( - RETURN CODE
LM R(,R12,2($R13& RESTORE R( "" R12
OI 1-$R13&,.3(13 MAR/ RETURNED
BR R14 RETURN TO CALLER
***********************************************************************
* MAINLINE STANDARD %2 BYTE SAE AREA *
***********************************************************************
SAE DC 1)F3(3
INITPARM DC A$INIT5&
TERMPARM DC A$TERM5&
SORTPARM DC A$SORT5&
*
ADDPARM DC (A$(&
DC A$ADD5&
ADDREC# DC A$(&
*
COUNTPRM DC (A$(&
DC A$COUNT5&
DC A$COUNTNUM&
*
RETRPRM DC (A$(&
DC A$RETRIE5&
DC A$RETRNUM&
DC A$DATAREC&
*
DWD DC D3(3
COUNTNUM DC F3(3
RETRNUM DC F3(3
*
INIT5 DC CL13I3
TERM5 DC CL13T3
ADD5 DC CL13A3
SORT5 DC CL13S3
COUNT5 DC CL13C3
RETRIE5 DC CL13R3
*
*EADER DC CL1333 3
ORG *EADER11
DC C3NUMBER OF RECORDS: 3
*EADNUM DC CL163 3
ORG ,
*
DATA DC CL1333 3
ORG DATA11
DC C3RECORD$3
DATANUM DC CL163 3
DC C3&: 3
DATAREC DC CL)(3 3
ORG ,
*
DC (D3(3,CL)3DCBS3
INDCB DCB DSORG=PS,MACRF=GL,LRECL=)(,RECFM=FB,DDNAME=INFILE, .
DCBE=INDCBE
OUTDCB DCB DSORG=PS,MACRF=PM,LRECL=133,RECFM=FBA,DDNAME=OUTFILE,
.
DCBE=OUTDCBE
INDCBE DCBE RMODE31=BUFF,EODAD=EOF
OUTDCBE DCBE RMODE31=BUFF
LTORG ,
ENDMAIN E,U *
DC (D3(3,CL)3RTN643
RTN64 DC (*3(3
***********************************************************************
* SUBROUTINE RTN64 - OPERATES IN 64 BIT MODE *
* *
* ENTRY IA: BASR R14,R1- FROM 24 OR 31 BIT MODE *
* *
* PARMS: R1 -2 PARMLIST $32-BIT& *
* $FUNCTION:C*AR$1&,P52, """ P5N& *
* *
* ON E.IT: R1- = RETURN CODE *
* REGISTERS R( "" R12 - RESTORED *
* R13 -2 SAE AREA SET/BIT$32& LOST *
* R14 = RETURN ADDRESS WIT* MODE *
* *
* FUNCTION: *
* 3I3 - INITIALI+E *
* 3T3 - TERMINATE *
* 3S3 - SORT *
* 3A3 - ADD RECORD *
* P52 : INPUT6RECORD:C*AR$)(& *
* 3C3 - RETURN T*E RECORD COUNT *
* P52 : RETURN T*E RECORD COUNT:BINARY$31& *
* 3R3 - RETRIEE T*E IT* RECORD *
* P52 : RECORD6NUMBER:BINARY$31& *
* P53 : RETURNED6RECORD:C*AR$)(& *
*=====================================================================*
* 64-BIT REGISTER DEFINITIONS *
***********************************************************************
G( E,U ( ----
G1 E,U 1 PARMLIST
G2 E,U 2 WOR/ REG
G3 E,U 3 WOR/ REG
G4 E,U 4 WOR/ REG
G- E,U - WOR/ REG
G6 E,U 6 WOR/ REG
G% E,U % WOR/ REG
G) E,U ) ----
G' E,U ' ----
G1( E,U 1( PARMLIST REGISTER
G11 E,U 11 STATIC PROGRAM BASE
G12 E,U 12 ----
G13 E,U 13 SAE AREA ADDRESS
G14 E,U 14 RETURN ADDRESS
G1- E,U 1- ENTRY/RETURN CODE
*
RECSI+E E,U )( SI+E OF A RECORD
***********************************************************************
* START PROCESSING IN CALLER3S MODE *
***********************************************************************
OLDSA13 USING SAER,R13
STM R14,R12,OLDSA13"SAGRS14 SAE REGISTERS R14 "" R12
STM* G1-,G1-,OLDSA13"SANE.T TEMP SAE *IG* G1-
LARL G1-,SAE64 G1- -2 NEW SAE AREA FORMAT -
NEWSA1- USING SAF-SA,G1- G1- : TEMP BASE TO NEW SAE
STM* G(,G14,NEWSA1-"SAF-SAG64*S( SAE *IG* G( "" G14
MC NEWSA1-"SAF-SAG64*S1-,OLDSA13"SANE.T
ST R1-,OLDSA13"SANE.T SET FORWARD C*AIN IN OLD SAE
LLGTR G2,R13 G2 -2 OLD SAE CLR *IG* ORDER
STG G2,NEWSA1-"SAF-SAPRE SAE 64-BIT PREIOUS SAE AREA
LLGTR G13,G1- G13-2 NEW SAE, CLEAR *IG*
DROP NEWSA1-,OLDSA13 RELEASE TEMP SAE BASE
CURSA13 USING SAF-SA,G13 G13 : CURRENT SAE AREA BASE
***********************************************************************
* SETUP ADDRESSABILITY AND PROCESS IN AMODE=64 *
***********************************************************************
SAM64 , GO TO 64 BIT MODE
!AS G11,PROCESS G11 -2 CURRENT ADDRESS
USING $*,ENDRTN64&,G11 G11 : PROGRAM BASE
CODE LOCTR ,
***********************************************************************
* GO TO FUNCTION RE,UESTED *
***********************************************************************
PROCESS DS (*
LLGTR G1(,R1 G1( -2 PARMLIST
LLGT G2,($,G1(& FETC* FUNCTION CODE
CLI ($G2&,C3A3 ADD A RECORD
!E ADD
CLI ($G2&,C3R3 RETRIEE A RECORD
!E RETRIEE
CLI ($G2&,C3C3 COUNT RECORDS
!E COUNT
CLI ($G2&,C3S3 SORT RECORDS
!E SORT
CLI ($G2&,C3I3 INITIALI+E REGION
!E INITIAL
CLI ($G2&,C3T3 TERMINATE REGION
!E TERMINAT
L*I R1-,16 UN/NOWN TYPE, RC = 16
! RETURN RETURN TO CALLER
***********************************************************************
* INITIALI+E RECORD AREA *
***********************************************************************
INITIAL DS (*
.GR G(,G( G( = (
STG G(,RECCNT SET RECORD COUNT = (
IAR64 RE,UEST=GETSTOR,SEGMENTS=SEGMENTS, .
GUARDLOC=*IG*,GUARDSI+E=GRDSI+E, .
RETCODE=RETCODE,RSNCODE=RSNCODE,ORIGIN=ORIGIN, .
MF=$E,IAR64&
ICM R1-,1-,RETCODE R1- = RETURN CODE
!+ RETURN IF RC = (, GOOD
! RC12 ELSE RETURN TO CALLER
***********************************************************************
* RETURN T*E COUNT OF RECORDS *
***********************************************************************
COUNT DS (*
LLGT G2,4$,G1(& G2 -2 RETURN COUNT
ICM R3,1-,RECCNT14 R3 = LOWER PART OF COUNT
ST R3,($,G2& SAE COUNT
!M RC() INDICATE COUNT OERFLOW
ICM* G3,1-,RECCNT FETC* TOP *ALF OF
!+ RC(( IF +ERO, O/
! RC() ELSE COUNT OERFLOW
***********************************************************************
* ADD A RECORD TO T*E ABOE T*E LINE ARRAY *
***********************************************************************
ADD DS (*
SAMRECG2 USING RECORD,G2
RTNRECG- USING RECORD,G-
LLGT G2,4$,G1(& G2 -2 INPUT RECORD
LG G3,RECCNT G- = NUMBER OF RECORDS
LG G4,ORIGIN G4 -2 ORIGIN
LGR G-,G3 G- = RECORD COUNT
MG*I G-,RECSI+E G- = OFFSET
LA G-,($G-,G4& G- -2 RECORD SLOT
MC RTNRECG-"CARD,SAMRECG2"CARD MOE IN RECORD
AG*I G3,1 BUMP RECORD COUNT
STG G3,RECCNT SAE ALUE
! RC(( RETURN TO CALLER
DROP RTNRECG-,SAMRECG2 RELEASE BASES
PUS* USING
***********************************************************************
* SORT T*E RECORDS *
***********************************************************************
SORT DS (*
LEAST USING RECORD,G2 G2 : LEAST RECORD
TOP USING RECORD,G4 G4 : CURRENT TOP
CURRENT USING RECORD,G- G- : CURRENT AT RECORD
LG G3,RECCNT G3 = NUMBER OF RECORD
LTGR G3,G3 DO WE *AE ANY 7
!NP RC(4 NO, RETURN
LG G4,ORIGIN G4 -2 ORIGIN
LG*I G6,RECSI+E G6 = SI+E OF RECORD
BCTGR G3,( G3 = RECORD COUNT - 1
MSGR G3,G6 G3 = MA.IMUM OFFSET
LA G%,TOP"RECORD$G3& G% -2 LAST RECORD
***********************************************************************
* OERALL RECORDS, SET T*E TOP FOR BUBBLE SORT *
***********************************************************************
SORTLP1 DS (*
LGR G2,G4 G2 -2 CURRENT LEAST
LGR G-,G4 G- -2 START
***********************************************************************
* LOO/ FOR T*E LEAST RECORD *
***********************************************************************
SORTLP2 DS (*
CLC CURRENT"CARD,LEAST"CARD TEST WIT* LEAST
!NL SORTN.2 IF STILL GREATER, S/IP
LA G2,CURRENT"RECORD ELSE SET NEW LEAST
SORTN.2 DS (*
!.LEG G-,G6,SORTLP2 GO TO NE.T ENTRY
***********************************************************************
* OPTIONALLY SWAP LEAST RECORD WIT* CURRENT TOP *
***********************************************************************
LA G(,LEAST"CARD G6 -2 LEAST RECORD
LA G1,TOP"CARD G% -2 TOP RECORD
CLGR G(,G1 ANY SWITC* 7
!E SORTN.1 NO, /EEP ASIS
.C LEAST"CARD,TOP"CARD ELSE SWAP RECORDS
.C TOP"CARD,LEAST"CARD """
.C LEAST"CARD,TOP"CARD """
***********************************************************************
* GO TO NE.T TOP RECORD *
***********************************************************************
SORTN.1 DS (*
!.LEG G4,G6,SORTLP1 GO TO NE.T ENTRY
! RC(( SORT COMPLETE
POP USING
***********************************************************************
* RETURN T*E IT* RECORD $ORIGIN NUMBER = (& *
***********************************************************************
RETRIEE DS (*
LLGT G2,4$,G1(& G2 -2 RECORD NUMBER TO RETRIEE
LGF G3,($,G2& G3 = RECORD NUMBER
LTGR G3,G3 TEST ALUE
!M RC() IF NEGATIE, ERROR
CG G3,RECCNT TEST WIT* CURRENT NUMBER
!NL RC() IF *IG*, RANGE ERROR
MG*I G3,RECSI+E G3 = OFFSET OF RECORD
ALG G3,ORIGIN G3 -2 RECORD
LLGT G2,)$,G1(& G2 -2 TARGET
SAMRECG2 USING RECORD,G2
RTNRECG3 USING RECORD,G3
MC SAMRECG2"CARD,RTNRECG3"CARD COPY IN RECORD
DROP RTNRECG3,SAMRECG2
! RC(( RETURN TO CALLER
***********************************************************************
* TERMINATE - REMOE T*E ABOE T*E BAR ARRAY *
***********************************************************************
TERMINAT DS (*
IAR64 RE,UEST=DETAC*,MEMOB!START=ORIGIN, .
RETCODE=RETCODE,RSNCODE=RSNCODE,MF=$E,IAR64&
ICM R1-,1-,RETCODE
!+ RETURN
! RC12
**********************************************************************
* RETURN TO CALLER IN MODE *
***********************************************************************
RC16 DS (*
L*I R1-,16
! RETURN
RC12 DS (*
L*I R1-,12
! RETURN
RC() DS (*
L*I R1-,)
! RETURN
RC(4 DS (*
L*I R1-,4
! RETURN
RC(( DS (*
.R R1-,R1-
RETURN DS (*
LG G2,CURSA13"SAF-SAPRE G2 -2 OLD SAE AREA
LA G3,CURSA13"SAF-SA G3 -2 CURRENT SAE
DROP CURSA13 RELEASE SAE AREA BASE
OLDSA2 USING SAER,R2 G2 : BASE TO PREIOUS SAE
CURSA3 USING SAF-SA,G3 G3 : CURRENT SAE AREA BASE
LM* G13,G1-,CURSA3"SAF-SAG64*S13 RESTORE *IG* G13 "" G1-
LR R13,R2 R13 -2 PREIOUS SAE
L R14,OLDSA2"SAGRS14 G14 = RETURN ADDRESS WIT* MODE
LMD G(,G12,CURSA3"SAF-SAG64*S(,OLDSA2"SAGRS(
DROP CURSA3,OLDSA2
BSM (,G14 RETURN TO CALLER
SAMPLE1 LOCTR ,
***********************************************************************
* FORMAT - SAE FOR RTN64 *
***********************************************************************
SAE64 DC .L$SAF-SA6LEN&3((3
ORG SAE641$SAF-SAID-SAF-SA&
DC A$SAF-SAID6ALUE&
ORG ,
SEGMENTS DC FD31(3
GRDSI+E DC F313
RETCODE DC F3(3
RSNCODE DC F3(3
ORIGIN DC AD$(&
RECCNT DC FD3(3
IAR64 MF=$L,IAR64&
LTORG ,
ENDRTN64 E,U *
***********************************************************************
* RECORD IMAGE *
***********************************************************************
RECORD DSECT ,
CARD DS CL$RECSI+E&
PUS* PRINT
PRINT NOGEN
***********************************************************************
* SYSTEM CONTROL BLOC/S *
***********************************************************************
I*ASAER ,
DCBD DED=DA,DSORG=PS
POP PRINT
END ,