Scribd
Upload
15K views

Verilog Code For Demux

This document provides the Verilog code and schematic diagram for a 1:4 demultiplexer (demux). The Verilog code defines a module with one input (a) and one select line (b) that outputs to a 4-bit bus (y). It uses NOT, AND gates to activate the appropriate output based on the input and select line values. The schematic diagram depicts the logic gate implementation of the 1:4 demux.

Uploaded by

meaow88
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
15K views

Verilog Code For Demux

This document provides the Verilog code and schematic diagram for a 1:4 demultiplexer (demux). The Verilog code defines a module with one input (a) and one select line (b) that outputs to a 4-bit bus (y). It uses NOT, AND gates to activate the appropriate output based on the input and select line values. The schematic diagram depicts the logic gate implementation of the 1:4 demux.

Uploaded by

meaow88
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

VERILOG CODE FOR 1:4DEMUX

module dem11(y,a,b);

output [3:0] y;

input a,b;

not(a_bar,a),(b_bar,b);

and(y[0],a_bar,b_bar),(y[1],a_bar,b),(y[2],a,b_bar),(y[3],a,b);

endmodule

(a)

(b)

FIG SCHEMATIC DIAGRAM FOR 1:4 DEMUX


FIG SCHEMATIC DIAGRAM FOR 1:4 DEMUX

You might also like