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    P45N02LD Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor

    Uploaded by

    Anonymous qrSsYuxyoY
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor in a TO-252 DPAK package. It lists absolute maximum ratings, thermal resistance ratings, electrical characteristics under static and dynamic conditions, source-drain diode ratings and characteristics, and mechanical data for the package dimensions. The key specifications include a drain-source breakdown voltage of 25V, on-state drain current of 45A at 10V gate-source voltage, and junction operating temperature range of -55 to 150 degrees Celsius.

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    © All Rights Reserved
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    P45N02LD Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor

    Uploaded by

    Anonymous qrSsYuxyoY
    81 views3 pages
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor in a TO-252 DPAK package. It lists absolute maximum ratings, thermal resistance ratings, electrical characteristics under static and dynamic conditions, source-drain diode ratings and characteristics, and mechanical data for the package dimensions. The key specifications include a drain-source breakdown voltage of 25V, on-state drain current of 45A at 10V gate-source voltage, and junction operating temperature range of -55 to 150 degrees Celsius.

    Original Description:

    elettronic

    Original Title

    P45N02LD

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    © © All Rights Reserved

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    This document provides specifications for an N-channel logic level enhancement mode field effect transistor in a TO-252 DPAK package. It lists absolute maximum ratings, thermal resistance ratings, electrical characteristics under static and dynamic conditions, source-drain diode ratings and characteristics, and mechanical data for the package dimensions. The key specifications include a drain-source breakdown voltage of 25V, on-state drain current of 45A at 10V gate-source voltage, and junction operating temperature range of -55 to 150 degrees Celsius.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    81 views3 pages

    P45N02LD Niko-Sem: N-Channel Logic Level Enhancement Mode Field Effect Transistor

    Uploaded by

    Anonymous qrSsYuxyoY
    This document provides specifications for an N-channel logic level enhancement mode field effect transistor in a TO-252 DPAK package. It lists absolute maximum ratings, thermal resistance ratings, electrical characteristics under static and dynamic conditions, source-drain diode ratings and characteristics, and mechanical data for the package dimensions. The key specifications include a drain-source breakdown voltage of 25V, on-state drain current of 45A at 10V gate-source voltage, and junction operating temperature range of -55 to 150 degrees Celsius.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    1

    MAY-24-2001
    N-Channel Logic Level Enhancement
    Mode Field Effect Transistor
    P45N02LD
    TO-252 (DPAK)
    NIKO-SEM

    ABSOLUTE MAXIMUM RATINGS (T
    C
    = 25 C Unless Otherwise Noted)
    PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
    Gate-Source Voltage V
    GS
    20 V
    T
    C
    =25 C 45
    Continuous Drain Current
    T
    C
    =100 C
    I
    D

    28
    Pulsed Drain Current
    1
    I
    DM
    140
    Avalanche Current I
    AR
    20
    A
    Avalanche Energy L =0.1mH E
    AS
    140
    Repetitive Avalanche Energy
    2
    L =0.05mH E
    AR
    5.6
    mJ
    T
    C
    =25 C 55
    Power Dissipation
    T
    C
    =100 C
    P
    D

    33
    W
    Operating J unction & Storage Temperature Range T
    j
    , T
    stg
    -55 to 150
    Lead Temperature (
    1
    /
    16
    from case for 10 sec.) T
    L
    275
    C

    THERMAL RESISTANCE RATINGS
    THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
    J unction-to-Case R
    J C
    3
    J unction-to-Ambient R
    J A
    70
    Case-to-Heatsink R
    CS
    0.7
    C / W
    1
    Pulse width limited by maximum junction temperature.
    2
    Duty cycle 1

    ELECTRICAL CHARACTERISTICS (T
    C
    = 25 C, Unless Otherwise Noted)
    LIMITS
    PARAMETER SYMBOL TEST CONDITIONS
    MIN TYP MAX
    UNIT
    STATIC
    Drain-Source Breakdown Voltage V
    (BR)DSS
    V
    GS
    =0V, I
    D
    =250A 25
    Gate Threshold Voltage V
    GS(th)
    V
    DS
    =V
    GS
    , I
    D
    =250A 0.8 1.2 2.5
    V
    Gate-Body Leakage I
    GSS
    V
    DS
    =0V, V
    GS
    =20V 250 nA
    V
    DS
    =20V, V
    GS
    =0V 25
    Zero Gate Voltage Drain Current I
    DSS

    V
    DS
    =20V, V
    GS
    =0V, T
    J
    =125 C 250
    A
    On-State Drain Current
    1
    I
    D(ON)
    V
    DS
    =10V, V
    GS
    =10V 45 A
    1. GATE
    2. DRAIN
    3. SOURCE
    PRODUCT SUMMARY
    V
    (BR)DSS
    R
    DS(ON)
    I
    D

    25 20m 45A
    G
    D
    S
    Free Datasheet http://www.datasheet4u.com/







    2
    MAY-24-2001
    N-Channel Logic Level Enhancement
    Mode Field Effect Transistor
    P45N02LD
    TO-252 (DPAK)
    NIKO-SEM
    V
    GS
    =7V, I
    D
    =18A 20 30
    Drain-Source On-State
    Resistance
    1

    R
    DS(ON)

    V
    GS
    =10V, I
    D
    =20A 15 28
    m
    Forward Transconductance
    1
    g
    fs
    V
    DS
    =15V, I
    D
    =30A 16 S
    DYNAMIC
    Input Capacitance C
    iss
    600
    Output Capacitance C
    oss
    290
    Reverse Transfer Capacitance C
    rss


    V
    GS
    =0V, V
    DS
    =15V, f =1MHz
    100

    pF
    Total Gate Charge
    2
    Q
    g
    25
    Gate-Source Charge
    2
    Q
    gs
    2.9
    Gate-Drain Charge
    2
    Q
    gd


    V
    DS
    =0.5V
    (BR)DSS
    , V
    GS
    =10V,
    I
    D
    =20A
    7.0

    nC
    Turn-On Delay Time
    2
    t
    d(on)
    7.0
    Rise Time
    2
    t
    r
    V
    DS
    =15V, R
    L
    =1 7.0
    Turn-Off Delay Time
    2
    t
    d(off)
    I
    D
    30A, V
    GS
    =10V, R
    GS
    =2.5 24
    Fall Time
    2
    t
    f
    6.0
    nS
    SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
    C
    = 25 C)
    Continuous Current I
    S
    45
    Pulsed Current
    3
    I
    SM
    150
    A
    Forward Voltage
    1
    V
    SD
    I
    F
    =I
    S
    , V
    GS
    =0V 1.3 V
    Reverse Recovery Time t
    rr
    37 nS
    Peak Reverse Recovery Current I
    RM(REC)
    I
    F
    =I
    S
    , dl
    F
    /dt =100A / S 200 A
    Reverse Recovery Charge Q
    rr
    0.043 C
    1
    Pulse test : Pulse Width 300 sec, Duty Cycle 2.
    2
    Independent of operating temperature.
    3
    Pulse width limited by maximum junction temperature.

    REMARK: THE PRODUCT MARKED WITH P45N02LD , DATE CODE or LOT #











    Free Datasheet http://www.datasheet4u.com/







    3
    MAY-24-2001
    N-Channel Logic Level Enhancement
    Mode Field Effect Transistor
    P45N02LD
    TO-252 (DPAK)
    NIKO-SEM

    TO-252 (DPAK) MECHANICAL DATA

    mm mm
    Dimension
    Min. Typ. Max.
    Dimension
    Min. Typ. Max.
    A 9.35 10.1 H 0.8
    B 2.2 2.4 I 6.4 6.6
    C 0.48 0.6 J 5.2 5.4
    D 0.89 1.5 K 0.6 1
    E 0.45 0.6 L 0.64 0.9
    F 0.03 0.23 M 4.4 4.6
    G 6 6.2 N

    Free Datasheet http://www.datasheet4u.com/

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