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couter: CLK en RST Out CLK RST Out

The document contains Verilog code that defines modules for a counter, a module to separate a 6-bit input into tens and ones place values, modules to drive 7-segment displays, and a top-level module to connect it all together to display a counting value on the 7-segment displays. It includes testbenches to simulate the behavior of the modules.

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Phạm HyuNa
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30 views4 pages

couter: CLK en RST Out CLK RST Out

The document contains Verilog code that defines modules for a counter, a module to separate a 6-bit input into tens and ones place values, modules to drive 7-segment displays, and a top-level module to connect it all together to display a counting value on the 7-segment displays. It includes testbenches to simulate the behavior of the modules.

Uploaded by

Phạm HyuNa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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//couter

module couter(input clk,en,rst,output reg[5:0] out);


always @(posedge clk)
begin
if(rst==0) out<=0;
else
begin
if(en)
if(out<59)out<=out+1;
else out<=0;
else
out<=out ;
end
end
endmodule

//tb_couter
module counter24test();
reg clk,rst,en;
wire [4:0] count;
couter dut(
.clk(clk),
.rst(rst),
.en(en),
.count(count));
initial
begin
clk=1;
rst=0;
en=0;
#4 en=1; //count=0
#10 rst=1;en=0;//count=0
#10 en=1; //count=1
end
always #5 clk=!clk;
endmodule

//set2
module set2(input [5:0]in,output reg[3:0]donvi,chuc);
always @(in)
begin
if(in<10 & in>=0)
begin
donvi=in;
chuc=0;
end
else if(in>9&in<20)
begin
chuc=1;
donvi=in-10;
end
else if(in>19&in<30)
begin
chuc=2;
donvi=in-20;
end

else if(in>29&in<40)
begin
chuc=3;
donvi=in-30;
end
else if(in>39 &in<50)
begin
chuc=4;
donvi=in-40;
end
else if(in>49&in<=59)
begin
chuc=5;
donvi=in-50 ;
end
else if(in<10)
begin
donvi=0;
chuc=0;
end
end
endmodule
//tb_set2
module tb_tachso();
reg [5:0]in;
wire [3:0]donvi,chuc;
tachso cst(.in(in),.donvi(donvi),.chuc(chuc));
initial
begin
in=0;
#5 in=1;
#5 in=2;
#5 in=3;
#5 in=4;
#5 in=5;
#5 in=6;
#5 in=7;
#5 in=8;
#5 in=9;
#5 in=10;
#5 in=11;
#5 in=24;
#5 in=45;
#5 in=57;
end
endmodule
//led7
module led7(input reg[3:0] in,output reg[6:0]out);
always @(in)
begin
if(in==0) out=7'b1111110;
else if(in==1) out=7'b0110000;
else if(in==2) out=7'b1101101;
else if(in==3) out=7'b1111001;
else if(in==4) out=7'b0110011;
else if(in==5) out=7'b1011011;
else if(in==6) out=7'b1011111;
else if(in==7) out=7'b1110000;
else if(in==8) out=7'b1111111;
else if(in==9) out=7'b1111011;
else out=0000000;

end
endmodule
//tb_seg7
module tb_led7();
reg [3:0]in;
wire [6:0]out;
seg7 cst(.in(in),.out(out));
initial
begin
in=0;
#5 in=1;
#5 in=2;
#5 in=3;
#5 in=4;
#5 in=5;
#5 in=6;
#5 in=7;
#5 in=8;
#5 in=9;
end
endmodule

//tonghop
module couter_top(
input clk,rst,en,
output [6:0] led1,led2);
wire [5:0] couter_out;
wire[3:0] donvi_out;
wire [3:0] chuc_out;
couter cnt1(
.clk(clk),
.rst(rst),
.en(en),
.out(couter_out)
);
set2 sp1(
.in(couter_out),
.donvi(donvi_out),
.chuc(chuc_out)
);
led7 seg_dv(
.in(donvi_out),
.out(led1)
);
led7 seg_chuc(
.in(chuc_out),
.out(led2)
);
endmodule
//tb_tonghop
module tb_tonghop();
reg clk,rst,en;
wire [6:0] led1,led2;
couter_top cst(
.clk(clk),
.rst(rst),

.en(en),
.led1(led1),
.led2(led2)
);
initial
begin
clk=1;
rst=0;
en=0;
#4 en=1; //count=0
#10 rst=1;en=0;//count=0
#10 en=1; //count=1
end
always #5 clk=!clk;
endmodule

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