Chapter 2

Datapath & Control

Subsystems
J in-Fu Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
J hongli, Taiwan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Introduction
Datapath Operators
Control Structures
Outline
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
System-Level Hierarchy
System (Top)
Complex units (cores)
Simple Components
Logic
Circuits
Silicon
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Categories of Components
Types of digital component
Datapath operators
Memory elements
Control structures
I/O interfaces
Tradeoff of selection
Speed
Density
Programmability
Easy of design
etc
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Composition of a Generic Digital Processor
I
n
p
u
t
/
O
u
t
p
u
t
Control
Memory
Datapath
Control
R
e
g
i
s
t
e
r
A
d
d
e
r
S
h
i
f
t
e
r
M
u
l
t
i
p
l
i
e
r
Bit 3
Bit 2
Bit 1
Bit 0
Data Input
Data Output
Bit-sliced datapath organization
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Datapath Adder
Adder Truth Table
C A B A.B(G) A+B(P) A B SUM CARRY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Generate Signal G(A.B): occurs when a carry output (CARRY)
is internally generated within the adder .
Propagate Signal P(A+B): when it is true, the carry in signal C is passed
to the carry output (CARRY) when C is true
A B
C
CARRY
G
P
SUM
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
Datapath Adder
-C
-A
-B
B
-A
C
C
-A
B
-B
-A
-C
SUM
A
A
A
A
A B C
SUM
SUM=A B C
CARRY=AB+AC+BC
Single-bit schematic of SUM
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Datapath Adder
Single-bit schematic of CARRY
C
A
B
A
B CARRY
-C
-A -B
CARRY
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
Datapath Adder
Optimized combinational adder schematic
C
i+1
=A
i
B
i
+A
i
C
i
+B
i
C
i
S
i
=(A
i
+B
i
+C
i
).C
i+1
+A
i
B
i
C
i
C
i
C
i+1
A
i
B
i
C
i
A
i
B
i
C
i+1
S
i
S
i
Vss
Vdd
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
Datapath Multiplexer-Based Full Adder
Adder Truth Table
Ci A B A B S Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
A
B
Ci
S
Cout
XNOR
XNOR
1
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Datapath Bit-Parallel Adder
Parallel adder implementations
S<n-1>
S<3>
S<2>
S<1>
S<0>
B<3>
B<2>
B<1>
B<0>
A<3>
A<2>
A<1>
A<0>
B<n-1>
A<n-1>
C<n>
C<n-1>
C<3>
C<0>
B<3>
B<2>
B<1>
B<0>
A<3>
A<2>
A<1>
A<0>
B<n-1>
A<n-1>
S<n-1>
S<3>
S<2>
S<1>
S<0>
C<0>
C<n-1>
C<3>
C<n>
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
Datapath Bit-Parallel Multiplexer-Based Adder
S<n-1>
S<1>
S<0>
B<1>
B<0>
A<1>
A<0>
B<n-1>
A<n-1>
C<n>
C<0>
XNOR
XNOR
1
0
XNOR
XNOR
1
0
XNOR
XNOR
1
0
C<1>
C<2>
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
Datapath Bit-Parallel Adder
S<3>
S<2>
S<1>
S<0>
B<3>
B<2>
B<1>
B<0>
A<3>
A<2>
A<1>
A<0>
C<3>
Vdd
S<3>
S<2>
S<1>
S<0>
B<3>
B<2>
B<1>
B<0>
A<3>
A<2>
A<1>
A<0>
C<3>
Subtract
A-B
If (Subtract==0)
{S=A+B;}
else
{S=A-B;}
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
Datapath Bit-Serial Adder
augend
addend
Result
Cout
Cin
A
B
0 1 1 0 1
0 1 0 0 1
1
1
1
0
0
0
0
0
1 0
1
1
0
0
1 1 0
0
1
1
1
0 1 1 0
0
0
0
0
1 0 1 1 0
1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
Datapath Carry Look-Ahead Adder (CLA)
Objective
To avoid the linear growth of the carry delay, we
use a Carry Look-Ahead Adder (CLA) in which
the carries can be generated in parallel
Feature
The Carry of each bit is generated from the
propagateand the generate signalsas well as the
input carry
The propagate and the generate signals are derived
from the operand A
i
and B
i
by
G
i
=A
i
.B
i
P
i
=A
i
+B
i
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Datapath Carry Look-Ahead Adder
CLG1 CLG2 CLG3 CLG4
SG1 SG2 SG3 SG4
S
0
S
1
S
2
S
3
C
0
C
1
C
2
C
3
C
4
P
0
P
0
-P
1
P
0
-P
2
P
0
-P
3
G
0
G
0
-G
1
G
0
-G
2
G
0
-G
3
C
i+1
=A
i
B
i
+(A
i
+B
i
)C
i
=G
i
+P
i
C
i
C
1
=G
0
+P
0
C
0
C
2
=G
1
+P
1
G
0
+P
1
P
0
C
0
C
3
=G
2
+P
2
G
1
+P
2
P
1
G
0
+P
2
P
1
P
0
C
0
C
4
=G
3
+P
3
G
2
+P
3
P
2
G
1
+P
3
P
2
P
1
G
0
+P
3
P
2
P
1
P
0
C
0
4-bit CLA
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Datapath Carry Look-Ahead Adder
CLG1
C
0
G
0
P
0
G
0
P
0
C
1
C
1
C
0
C
0
G
0
P
0
G
0
P
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Datapath Carry Look-Ahead Adder
CLG4
C
4
G
0
G
1
G
2
G
3
P
0
P
1
P
2
P
3
C
0
C
4
=G
3
+P
3
G
2
+P
3
P
2
G
1
+P
3
P
2
P
1
G
0
+P
3
P
2
P
1
P
0
C
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
Datapath Carry Look-Ahead Adder
Manchester Carry Chain
C
i+1
=G
i
+P
i
C
i
G
i
=A
i
.B
i
P
i
=A
i
+B
i
Introduce the carry-kill bit K
i,
this term gets its name from the fact that if
K
i
=1, then P
i
=0 and G
i
=0, so that C
i+1
=0; K
i
=1 thus kills the carry-out
bit.
K
i
=A
i
.B
i
C
i+1
C
i
G
i
K
i
P
i A
i
B
i
P
i
G
i
K
i
0 0 0 0 1
0 1 1 0 0
1 0 1 0 0
1 1 0 1 0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
Datapath Carry Look-Ahead Adder
Manchester circuit styles
C
i+1
C
i
G
i
G
i
P
i
P
i
C
i+1
C
i
G
i
P
i
Clk
Static circuit
Dynamic circuit
G
3
P
3
G
2
P
2
G
1
P
1
G
0
P
0
C
0
Clk
Clk
C
4
C
4
C
3
C
2
C
1
Dynamic Manchester chain
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
Datapath Carry Look-Ahead Adder
Extension to wide adders
If we use a brute-force approach for an 8-bit design, then the
carry-out bit C
8
would have a term of the form
0 0 1 2 3 4 5 6 7
C P P P P P P P P
Multilevel CLA networks can improve this problem
n-bit adder
bit[0] bit[n-1]
[i] [i+3]
4-bit CLG
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
Datapath Carry Look-Ahead Adder
4-bit Carry Lookahead Generator
G
i
P
i
G
i+1
P
i+1
G
i+2
P
i+2
G
i+3
P
i+3
C
i+1
C
i+2
C
i+3
G
[i,i+3]
P
[i,i+3]
block generate
block propagate
G
[i
,
i+3]
=G
i+3
+P
i+3
G
i+2
+P
i+3
P
i+2
G
i+1
+P
i+3
P
i+2
P
i+1
G
i
P
[i
,
i+3]
=P
i+3
P
i+2
P
i+1
P
i
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
Datapath Carry Look-Ahead Adder
A 16-bit two-level CLA
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Datapath Carry-Skip Adder
4-bit adder
c
i+4
A carry-skip adder is designed to speed up a wide adder by aiding
the propagation of a carry bit around a portion of the entire adder.
[i+3] [i]
c
i
P
[i,i+3]
c
i+4
+c
i
.P
[i,i+3]
k-bit adder
c
i
Carry-skip
Carry-skip logic Generalization
c
i+k
P
[i,i+3]
=P
i+3
P
i+2
P
i+1
P
i
Carry=C
i+4
+P
[i,i+3]
C
i
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
Datapath Carry-Select Adder
b
7
a
7
b
6
a
6
b
5
a
5
b
4
a
4
b
7
a
7
b
6
a
6
b
5
a
5
b
4
a
4
b
3
a
3
b
2
a
2
b
1
a
1
b
0
a
0
4-bit adder L
4-bit adder U0 4-bit adder U1
MUX MUX MUX MUX
1 0 1 0 1 0 1 0
MUX
1 0
c
0
c=0 c=1
c
8
s
7
s
6
s
5
s
4
s
7
s
6
s
5
s
4
s
7
s
6
s
5
s
4
c
8
c
4
c
8
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
Datapath Conditional-Sum Adder
A
0
B
0
C
0
=C
in
Conditional
cell
S
0
S
1
C
0
C
1
A
1
B
1
Conditional
cell
S
0
S
1
C
0
C
1
A
2
B
2
Conditional
cell
S
0
S
1
C
0
C
1
A
3
B
3
Conditional
cell
S
0
S
1
C
0
C
1
C
4
S
0
S
1
S
2
S
3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
Datapath 8-bit Conditional-Sum Adder
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
Datapath Hybrid CLA-CSA
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
Datapath Shifter
Left Nop Right
A
i
A
i-1
B
i
B
i-1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
Datapath Barrel Shifter
A
3
B
3
A
2
B
2
A
1
B
1
A
0
B
0
Sh
0
Sh
1
Sh
2
Sh
3
Sh
1
Sh
2
Sh
3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
Datapath Multipliers
a
a b axb
0
0
0
1
0 0
0 1
1 0
1 1
b
axb
Bit-level multiplier
a
3
Multiplication of two 4-bit words
a
2
a
1
a
0
b
3
b
2
b
1
b
0
a
0
b
0
a
1
b
0
a
2
b
0
a
3
b
0
a
0
b
1
a
1
b
1
a
2
b
1
a
3
b
1
a
0
b
2
a
1
b
2
a
2
b
2
a
3
b
2
a
0
b
3
a
1
b
3
a
2
b
3
a
3
b
3
p
3
p
2
p
1
p
0
p
7
p
6
p
5
p
4
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
Datapath Multipliers
The product axb is given by the 8-bit result
p=p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0

k j i
i k j i
c b a p
1
The ith product term p
i
can be expressed as
Alternate view of multiplication process
a
3
a
2
a
1
a
0
b
3
b
2
b
1
b
0
a
0
) a
1
a
2
(a
3
p
3
p
2
p
1
p
0
p
7
p
6
p
5
p
4
xb
0
a
0
) a
1
a
2
(a
3
xb
1
a
0
) a
1
a
2
(a
3
xb
2
a
0
) a
1
a
2
(a
3
xb
3
(axb
0
)2
0
(axb
1
)2
1
(axb
2
)2
2
(axb
3
)2
3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
Datapath Multipliers
(axb
0
)2
0
(axb
1
)2
1
(axb
2
)2
2
(axb
3
)2
3
7
6 5 4 3 2 1 0 Product register
Using a product register for multiplication
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
Datapath Multipliers
add (axb
0
)
shift right
a
3
b
0
Shift-right multiplication sequence
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
c
x
c
x
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
c
y
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
c
y
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
a
2
b
2
a
1
b
2
a
0
b
2
a
3
b
2
a
2
b
3
a
1
b
3
a
0
b
3
a
3
b
3
p
7
add (axb
1
)
shift right
add (axb
2
)
shift right
add (axb
3
)
shift right
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
Datapath Register-Based Multiplier
Multiplicand
MUX
n-bit adder
Multiplier
Product register (2n)
n n
n
n
n
clk
shr
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
Datapath Array Multipliers

1
0
2
n
i
i
i
X X

1
0
2
n
j
j
j
Y Y

1
0
1
0
2 2
n
i
n
j
j
j
i
i
Y X Y X P
Consider two unsigned binary integers X and Y

1
0
1
0
1
0
2
2 ) (
n n
k
k
k
n
j
j i
j i
n
i
P
Y X
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37
Datapath Array Multipliers
X
3
Y
0
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
X
2
Y
0
X
1
Y
0
X
0
Y
0
X
3
Y
1
X
2
Y
1
X
1
Y
1
X
0
Y
1
X
3
Y
2
X
2
Y
2
X
1
Y
2
X
0
Y
2
X
3
Y
3
X
2
Y
3
X
1
Y
3
X
0
Y
3
0 0 0
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38
Datapath Array Multipliers
X
3
X
2
X
1
X
0
Y
0
Y
1
Y
2
Y
3
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39
Booths algorithm takes advantages of the fact that an
adder-substractor is nearly as fast and small as a simple
adder
Consider the twos complement representation of the
multiplier y

The representation can be rewritten as

Extract the first two terms

The right-hand term can be used to add x to partial

product
The left-hand term add 2x
Datapath Booth Multiplier

2
2
1
1
2 2 2
n
n
n
n
n
n
y y y y

) ( 2 ) ( 2 ) ( 2
2 3
2
1 2
1
1 n n
n
n n
n
n n
n
y y y y y y y
) ( 2 ) ( 2
1 2
1
1

n n
n
n n
n
y y y y y
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40
Datapath Booth Multiplier
2 1 i i i
y y y
Operation
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Add 0
Add x
Add x
Add 2x
Sub 2x
Sub x
Sub x
Add 0
Actions during Booth multiplication
For example, x=011001 (25
10
), y=101110 (-18
10
)
1. y
1
y
0
y
-1
=100, so P
1
=P
0
-2x.1=11111001110
2. y
3
y
2
y
1
=111, so P
2
=P
1
+0.4=11111001110
3. y
5
y
4
y
3
=101, so P
3
=P
2
-x.16=11000111110
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41
Datapath Booth Multiplier
Structure of a Booth multiplier
left shift 2
code
Mux sel
Adder/substractor
P
j+2
P
j+1
y
i+4
y
i+3
y
i+2
Stage j+1 2x x
0
left shift 2
code
Mux sel
Adder/substractor
P
j+1
P
j
y
i+2
y
i+1
y
i
Stage j 2x x
0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42
Datapath Wallace Tree Multiplier
A Wallace tree is a full adder tree structured
specially for a quick addition of the partial products
Example
A 16x16 Booth multiplier
8 partial products are generated
Assume that all partial products are negative so all sign
extension bits are 1s
Sign extension correction vector is 1010101010101011
1111111111111111
11111111111111
111111111111
1111111111
11111111
111111
1111
11
1010101010101011
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43
Datapath Wallace Tree Multiplier
Wallace tree multiplication
1st stage
4-2 compression
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
2nd stage
4-2 compression
Sign Extension
Correction
Final Addition
Partial
Products
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44
Datapath Wallace Tree Multiplier
4-2 compressor Carry-save adder
FA
FA
c s
FA FA
Inputs
Outputs
FA
c s
FA
c s
FA
c s
C
out
C
in
C
out
C
in
Inputs
Outputs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45
Datapath Serial Multiplication
X
Y
reset
serial register
Serial multiplier
1. Require MN clock cycles to produce a product for an N-bit
multiplier and a M-bit multiplicand
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46
Datapath Serial Multiplication
X
Y
0
Serial/parallel multiplier
D D D
D D D
Y
1
Y
2
Y
3
S
0
S
1
S
2
1. Require M+N clock cycles to produce a product for an N-bit
multiplier and a M-bit multiplicand
2. The critical path consists of the adders
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47
Control FSM
output
clk
input
output
clk
input
Moore
Mealy
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48
Control FSM
FSM design procedure
Draw the state-transition diagram
Check the state diagram
Write state equations (Write HDL)
An example of state-transition diagram
IDLE
WAIT
EXIT
A
IDLE: (S1,S0)=(00)
WAIT: (S1,S0)=(01)
EXIT: (S1,S0)=(10)
A: car-in
C: change-ok
R: rst
R
-A
A
-A
C
-C
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49
Control FSM
Check the state-transition diagram
Ensure all states are represented, including the IDLE
state
Check that the OR of all transitions leaving a state is
TRUE. This is a simple method of determining that
there is a way out of a state once entered.
Verify that the pairwise XOR of all exit transitions is
TRUE. This ensures that there are not conflicting
conditions that would lead to more than one exit-
transition becoming active at any time.
Insert loops into any state if it is not guaranteed to
otherwise change on each cycle.
Formal FSM verification method
Perform conformance checking
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50
Control Verilog Coding Style for FSMs
module
toll_booth(clk,rst,car_in,change_ok,green);
input clk,rst,car_in,change_ok;
output green;
reg[1:0] state_reg, next_state;
parameter IDLE =2b00;
parameter WAIT =2b01;
parameter EXIT =2b11;
always @(posedge clk or posedge rst) begin
If (rst==1b1) state_reg<=IDLE;
else state_reg<=next_state;
end
always @(state_reg or car_in or change_ok)
begin
case(state_reg):
IDLE: if (car_in==11) begin
next_state=WAIT;
green=1b0;
end else begin
next_state=IDEL;
end
WAIT: if (change==1b1) begin
next_state=EXIT;
green=1b1;
end else begin
next_state=WAIT;
green=1b0;
end
EXIT: if (car_in==11) begin
next_state=EXIT;
green=1b1;
end else begin
next_state=IDEL;
green=1b0;
end
default: begin
next_state=IDLE;
green=1b0;
end
endcase
end
endmodule
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51
Control PLA

i
i i
d c b a m f ) , , , (
Structure of a PLA
AND array OR array
a b c d f
0
f
1
f
2
f
3
Minterms
d c b a d c b a d c b a f
1
A PLA represents an expression of sum-of-product (SOP)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52
Control PLA
a b c d f
0
f
1
f
2
f
3
Fuse-programmable PLA
Fuse
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53
Control PLA
a b c d f
0
f
1
f
2
f
3
Logic gate diagram of a PLA