CPU Organisation & Operation

Professor Kin K. Leung

[email protected]
www.commsp.ee.ic.ac.uk/~kkleung/

Heavily based on materials by Dr. Naranker Dulay

Computer Architecture (K.K. Leung) CPU Organisation & Operation (1)

Fetch-Execute Cycle
 Fetch the Instruction

 Increment the Program Counter

 Decode the Instruction

 Fetch the Operands

 Perform the Operation

 Store the Results

 Repeat Forever
Computer Architecture (K.K. Leung) CPU Organisation & Operation (2)
High-Level/Low-Level Languages, Machine Code

 High-Level Language (e.g. Java, C++, Haskell)

A=B+C Assignment Statement

 Low-Level Language -> Assembly Language (e.g. Pentium, PowerPC,

ARM etc, Java Bytecode)

LOAD R2, B Assembly Language

ADD R2, C Instructions
STORE R2, A

 (Binary) Machine Code

0001101000000001 Machine Code

0011101000000010 Instructions
0010101000000000
Computer Architecture (K.K. Leung) CPU Organisation & Operation (3)
The Toy1 Architecture
 Maximum of 1024 x 16-bit memory words
Memory is Word Addressed

 Two’s Complement Integer Representation

 4 General Purpose Registers (16-bit) : R0, R1, R2, R3

 Upto 16 “Instructions”, e.g. LOAD, ADD, STORE

Computer Architecture (K.K. Leung) CPU Organisation & Operation (4)

Toy1 Instruction Set
 LOAD Register , [MemoryAddress]
Register = Memory [MemoryAddress]

 STORE Register , [MemoryAddress]

Memory [MemoryAddress] = Register

 ADD Register , [MemoryAddress]

Register = Register + Memory [MemoryAddress]

 SUB Register , [MemoryAddress]

Register = Register - Memory [MemoryAddress]

Computer Architecture (K.K. Leung) CPU Organisation & Operation (5)

Toy1 Instruction Format

Assembly Instruction e.g. ADD R2, C

Machine Code OPCODE REG ADDRESS

4-bit 2-bit 10-bit

Instruction Fields
 OPeration CODE (Selects CPU Instruction)
 REGister (Specifies 1st Operand for Instruction)
 ADDRESS (Specifies 2nd Operand for Instruction)

Computer Architecture (K.K. Leung) CPU Organisation & Operation (6)

Other Possibilities for the Format

ADD R2, C OPCODE ADDRESS REG

4-bit 10-bit 2-bit

REG ADDRESS OPCODE

2-bit 10-bit 4-bit

ADD R2, R3 OPCODE REG REG OPCODE REG REG

4-bit 2-bit 2-bit 4-bit 2-bit 2-bit

Computer Architecture (K.K. Leung) CPU Organisation & Operation (7)

Instruction Field Encoding
OPCODE REG ADDRESS
4-bit 2-bit 10-bit 16-bit Instruction

 OPCODE LOAD 0001

(4-bit) STORE 0010
ADD 0011
SUB 0100
 REG Register 0 00
(2-bit) Register 1 01
Register 2 10
Register 3 11
 ADDRESS 10-bit Memory Word Address
Computer Architecture (K.K. Leung) CPU Organisation & Operation (8)
Memory Placement (Program)
Assembly Machine Instruction Memory
Instruction OP REG ADDRESS Address

LOAD R2, [201H] 0001 10 10 0000 0001 00 1000 0000

1 A 0 1 0 8 0 H

ADD R2, [202H] 0011 10 10 0000 0010 00 1000 0001

3 A 0 2 0 8 1 H

STORE R2, [200H] 0010 10 10 0000 0000 00 1000 0010

2 A 0 0 0 8 2 H

MEMORY
Computer Architecture (K.K. Leung) CPU Organisation & Operation (9)
Memory Placement (Data)
Assembly Data Memory
Instruction Address

A=0 0000 0000 0000 0000 10 0000 0000

0 0 0 0 2 0 0 H

B=9 0000 0000 0000 1001 10 0000 0001

0 0 0 9 2 0 1 H

C=6 0000 0000 0000 0110 10 0000 0010

0 0 0 6 2 0 2 H

MEMORY
Computer Architecture (K.K. Leung) CPU Organisation & Operation (10)
CPU Organisation
CPU R0 000
R1 Address 001
Bus 002
R2 I 003
R3 n
t
ALU e
Input Reg1 Data
r Bus
Output Reg RAM
n
Input Reg2 a
l
Control
Program Counter B Bus
u
Instr. Decoder Instr. Register s
3FD
3FE
Control Unit 3FF

Computer Architecture (K.K. Leung) CPU Organisation & Operation (11)

LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

080H
RAM

080H
PC 080H 0
Instr. Decoder
3FD
0
0 3FE
Control Unit 3FF
1
Computer Architecture (K.K. Leung) CPU Organisation & Operation (12)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

PC 080H + 1 0
Instr. Decoder
3FD
3FE
Control Unit 3FF
2
Computer Architecture (K.K. Leung) CPU Organisation & Operation (13)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H 002
R2 003

ALU

RAM

0
PC 081H
Instr. Decoder
3FD
3FE
Control Unit 3FF
3
Computer Architecture (K.K. Leung) CPU Organisation & Operation (14)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
080H
R2
080 1A01H
1A01
081 3A02H
ALU 082 2A00H

RAM

200 0000
0 201 0009
PC 081H 202 0006

Instr. Decoder
3FD
3FE
Control Unit 3FF
4
Computer Architecture (K.K. Leung) CPU Organisation & Operation (15)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
001
201H
R2
080 1A01H
081 3A02H

201H
ALU 082 2A00H
1A01H 1A01
RAM

1A01H
200 0000
201 0009
PC 081H 0 202 0006
1A01H
1A01H 1A01H
3FD
0
1, 2, 201H 201H 3FE
1, 2, 201H 3FF
0 5
Computer Architecture (K.K. Leung) CPU Organisation & Operation (16)
LOAD R2, [201H] R2=Memory[201H]
CPU 000
201H 001
0009 201H
R2 0009
080 1A01H
081 3A02H

0009
ALU 082 2A00H
0009 0009
RAM

200 0000
0 201 0009
PC 081H 0 202 0006

1A01H
3FD
3FE
1, 2, 201H 3FF
6
Computer Architecture (K.K. Leung) CPU Organisation & Operation (17)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H

081H
ALU 082 2A00H

RAM

200 0000
081H 201 0009
PC 081H 0 202 0006

3FD
0 0 3FE
3FF
7
Computer Architecture (K.K. Leung) CPU Organisation & Operation (18)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
081H
R2 0009
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 081H + 1 0 202 0006

3FD
3FE
3FF
8
Computer Architecture (K.K. Leung) CPU Organisation & Operation (19)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
202H 081H
0009
R2 0009
0009

202H 0009
080 1A01H
081 3A02H
3A02
ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM

3A02H
200 0000
201 0009
PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
3FD
0
3, 2, 202H 202H 3FE
3, 2, 202H 3FF
0 9
Computer Architecture (K.K. Leung) CPU Organisation & Operation (20)
ADD R2, [202H] R2=R2+Memory[202H]
CPU 000
001
000FH 202H 202H
R2 000FH
0009
080

000FH
1A01
081 3A02
ALU 082 2A00
0009 0006 0006
000FH ADD RAM

000FH
0006
000FH 0006
200 0000
201 0009
PC 082H 0 0 202 0006

3A02H
3FD
3FE
3, 2, 202H 3FF
10
Computer Architecture (K.K. Leung) CPU Organisation & Operation (21)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H
081 3A02H

082H
ALU 082 2A00H

RAM

200 0000
082H 201 0009
PC 082H 0 202 0006

3FD
0 0 3FE
3FF
11
Computer Architecture (K.K. Leung) CPU Organisation & Operation (22)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
082H
R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H

RAM

200 0000
201 0009
PC 082H + 1 0 202 0006

3FD
3FE
3FF
12
Computer Architecture (K.K. Leung) CPU Organisation & Operation (23)
STORE R2, [200H] Memory[200H]=R2
CPU 000
001
200H 082H
000FH
R2 000FH
000F

200H 000FH
080 1A01H
081 3A02H
ALU 082 2A00H
2A00
000FH 2A00H
RAM

2A00H
200 0000
201 0009
PC 083H 1 1 202 0006
2A00H
2A00H 2A00H
3FD
1
2, 2, 200H 200H 3FE
2, 2, 200H 3FF
1 13
Computer Architecture (K.K. Leung) CPU Organisation & Operation (24)
STORE R2, [200H] Memory[200H]=R2
CPU 000
200H 200H 001

R2 000FH
080 1A01H
081 3A02H
ALU 082 2A00H
00FH 00FH
RAM

200 000FH
0000
1 1 201 0009
PC 083H 202 0006

3FD
3FE
3FF
14
Computer Architecture (K.K. Leung) CPU Organisation & Operation (25)