Scribd
Upload
42 views5 pages

March Test

This document describes a memory test experiment with three modules: 1. A mem_stte module that implements a dual-port memory using a single RAM block and allows reading and writing data through ports 1 and 2. 2. A cnt_8 counter module that increments or decrements a 4-bit counter on each clock edge. 3. A top_module that instantiates the mem_stte and cnt_8 modules and connects their inputs and outputs to form a system that can write data to memory using a counter as the address.

Uploaded by

jeshkakkad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
42 views5 pages

March Test

This document describes a memory test experiment with three modules: 1. A mem_stte module that implements a dual-port memory using a single RAM block and allows reading and writing data through ports 1 and 2. 2. A cnt_8 counter module that increments or decrements a 4-bit counter on each clock edge. 3. A top_module that instantiates the mem_stte and cnt_8 modules and connects their inputs and outputs to form a system that can write data to memory using a counter as the address.

Uploaded by

jeshkakkad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Experiment 9

Memory test

module mem_stte(
input clk_1,clk_2,
input [7:0] data_in_1,data_in_2,
input [3:0] address_1,
input [3:0] address_2,
input en_1,
input en_2,
input wr_1,wr_2,
output reg [7:0] data_out_1,
output reg [7:0] data_out_2
);
parameter RAM_WIDTH = 8;
parameter RAM_ADDR_BITS = 4;
reg [RAM_WIDTH-1:0] ram1 [(2**RAM_ADDR_BITS)-1:0];
always @(posedge clk_1)
if (en_1) begin
if (wr_1)
ram1[address_1] <= data_in_1;
data_out_1 <= ram1[address_1];
end

always @(posedge clk_2)
if (en_2) begin
if (wr_2)
ram1[address_2] <= data_in_2;
data_out_2 <= ram1[address_2];
end
endmodule



counter 4 bit

module cnt_8(
input rst,
input en,
input clk,
input u_d,
output [3:0] cnt_out
);
reg [3:0] cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= 0;
else if (en)
if (u_d)
cnt <= cnt + 1;
else
cnt <= cnt - 1;
end
assign cnt_out = cnt;
endmodule

main module
module top_module(
input clk,
input rst,
input en_1,
input en_2,
input en_cnt,
input u_d,
input wr_1,wr_2,
input [7:0] data_in1,data_in2,
output [7:0] data_out_1,
output [7:0] data_out_2
);
wire [3:0] int_cm;
cnt_8 x1( rst,en_cnt,clk,u_d,int_cm);
mem_stte x2 ( clk,clk,data_in1,data_in2,int_cm,int_cm,en_1,en_2,wr_1,wr_2,data_out_1,data_out_2);


endmodule








Test bench waveform






simulatio

You might also like