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Sequential 4-Bit Adder: Project Requirements

This document outlines the requirements for a project to design a sequential 4-bit adder circuit. It specifies that the project should be completed by teams of 3-4 individuals and include: a report of no more than 25 pages discussing the design issues and verification, timing diagrams from transient analysis, the final circuit layout, and post-layout simulations. The circuit must add 4-bit inputs A and B sequentially on each clock cycle, with outputs for the sum S and carry Co. Timing will be provided by voltage pulse sources and the design must operate at 2GHz with rise/fall times of 100ps and a load capacitance of 20fF.

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Hossein Sobhanifar
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34 views1 page

Sequential 4-Bit Adder: Project Requirements

This document outlines the requirements for a project to design a sequential 4-bit adder circuit. It specifies that the project should be completed by teams of 3-4 individuals and include: a report of no more than 25 pages discussing the design issues and verification, timing diagrams from transient analysis, the final circuit layout, and post-layout simulations. The circuit must add 4-bit inputs A and B sequentially on each clock cycle, with outputs for the sum S and carry Co. Timing will be provided by voltage pulse sources and the design must operate at 2GHz with rise/fall times of 100ps and a load capacitance of 20fF.

Uploaded by

Hossein Sobhanifar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sequential 4-bit adder

(project - 25% of the final mark)


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Project requirements:
Teams of 3-4 individuals;
out3
Project report no more than 25 pages and include:
out2
o the discussion and verification of the design issues,
o timing diagrams from transient analysis,
o layout of the final circuit,
o post layout simulations of the final circuit;
J "2IGHz (clock p e r i o ~ lOOOps);
tJise, t_fall=lOOps (by setting the vpulse properties);
CL=20fF;
maximize figure of merit FOM = J(GHz)
P(,uW)
Project description:
Timing for clocks will be provided by vpulse sources in Cadence.
Sequential 4-bit adder should add bits Ai and Bi in the following order:
Co and S signals are as follows (Rabaey)
Co = AB + BC; + A C;
out1
S=AEBBEBC,. =ABC+ABC.+ABC+ABC =ABC+C (A+B+C)
I I r I 1 0 I
Design the circuit and demonstrate the timing diagram for A, B, clk's and out.
outO

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