LecLure 7: Memory ManagemenL

CSL 120: rlnclples of Cperaung SysLems

uC San ulego: Summer Sesslon l, 2009
lrank uyeda
AnnouncemenLs
eerWlse quesuons due Lomorrow.
ro[ecL 2 ls due on lrlday.
MllesLone on 1uesday nlghL.
Pomework 3 ls due nexL Monday.
2
Coals for 1oday
Mouvauon for Memory ManagemenL
undersLand aglng
Pow Lo LranslaLe from vlrLual Lo physlcal address
ueLermlne slze, sLrucLure of page Lables
3
Memory ManagemenL
Coals of memory managemenL
rovlde a convenlenL absLracuon for programmlng
AllocaLe scarce memory resources among compeung
processes
Maxlmlze performance wlLh mlnlmal overhead
Mechanlsms
hyslcal and vlrLual addresslng
1echnlques: aruuonlng, paglng, segmenLauon
age Lable managemenL, 1L8s, vM Lrlcks
ollcles
age replacemenL algorlLhms
4
ln Lhe beglnnlng...
8aLch programmed sysLems
rograms use physlcal
addresses dlrecLly
CS loads [ob, runs lL, unloads lL
Slmllar Lo whaL nachos does
rlghL now
(you'll change Lhls ln ro[ecL 2)
3
SLack
Peap
uaLa SegmenL
1exL SegmenL
S
C
Cperaung SysLem
!"#$%&'( *+,-.#
LeL Lhere be Muluprogrammlng
Muluprogrammlng changes all of Lhls
WanL muluple processes ln memory aL once
Cverlap l/C and Cu of muluple [obs
Can do lL a number of ways
llxed and varlable paruuonlng, paglng, segmenLauon
8equlremenLs
need proLecuon - resLrlcL whlch addresses [obs can use
lasL Lranslauon - lookups need Lo be fasL
lasL changes - updaung memory hardware on conLexL
swlLch
6
vlrLual Memory
1he baslc absLracuon provlded by Lhe CS memory
managemenL ls vlrLual memory
A process's address space ln memory ls noL necessarlly
Lhe same as Lhe physlcal memory (8AM) address ln whlch
lL resldes
When a process requesLs a memory address, Lhe CS wlll
LranslaLe Lhe address from a vlrLual address Lo a physlcal
address.
7
vlrLual Addresses
rocesses access memory uslng a vlrLual address
1he vlrLual address ls noL Lhe same as Lhe physlcal 8AM address ln whlch lL resldes
1he CS (hardware MMu) LranslaLes Lhe vlrLual address lnLo Lhe physlcal 8AM address
Who deLermlnes Lhe mapplng for Lhe Lranslauon?
8
SLack
Peap
uaLa SegmenL
1exL SegmenL
S
C
0x00... (SLarung Address)
0xlll... (Lndlng Address)
/00.+$$ 12'&+
vlrLual Addresses
rocesses access memory uslng a vlrLual address
1he vlrLual address ls noL Lhe same as Lhe physlcal 8AM address ln whlch lL resldes
1he CS (hardware MMu) LranslaLes Lhe vlrLual address lnLo Lhe physlcal 8AM address
Who deLermlnes Lhe mapplng for Lhe Lranslauon?
9
SLack
Peap
uaLa SegmenL
1exL SegmenL
S
C
0x00... (SLarung Address)
0xlll... (Lndlng Address)
/00.+$$ 12'&+
SLack
Peap
uaLa SegmenL
1exL SegmenL
!"#$%&'( *+,-.#
MMu
.
.
.

3%.45'( *+,-.#
vlrLual Addresses
rocesses access memory uslng a vlrLual address
1he vlrLual address ls noL Lhe same as Lhe physlcal 8AM address ln whlch lL resldes
1he CS (hardware MMu) LranslaLes Lhe vlrLual address lnLo Lhe physlcal 8AM address
Who deLermlnes Lhe mapplng for Lhe Lranslauon?
10
SLack
Peap
uaLa SegmenL
1exL SegmenL
S
C
0x00... (SLarung Address)
0xlll... (Lndlng Address)
/00.+$$ 12'&+
SLack
Peap
uaLa SegmenL
1exL SegmenL
!"#$%&'( *+,-.#
MMu
.
.
.

3%.45'( *+,-.#
vlrLual Memory
vlrLual memory enables programs Lo execuLe wlLhouL
requlrlng Lhelr enure address space reslde ln physlcal memory
Saves space
Many programs do noL need all of Lhelr code and daLa aL once (or ever),
so Lhere ls no need Lo allocaLe memory for lL
Allows exlblllLy for appllcauon and CS
lndlrecuon allows movlng programs around ln memory, CS can ad[usL
amounL of memory allocaLed based upon lLs run-ume behavlor
Allows processes Lo address more !" less memory Lhan physlcally lnsLalled
ln Lhe machlne
lsolauon and proLecuon
Cne process cannoL access memory addresses ln oLhers
Lxcepuon: shared memory, whlch we've already covered
11
Memory ManagemenL 8equlremenLs
roLecuon
8esLrlcL whlch physlcal addresses processes can use, so
Lhey can'L sLomp on each oLher
lasL Lranslauon
Accesslng memory musL be fasL, regardless of Lhe
proLecuon scheme
lasL conLexL swlLchlng
Cverhead of updaung memory hardware on a conLexL
swlLch musL be low
8equlres hardware supporL for emclenL lmplemenLauon
12
MMu and 1L8
Memory ManagemenL unlL (MMu)
Pardware unlL LhaL LranslaLes a vlrLual address Lo a physlcal address
Lach memory reference ls passed Lhrough Lhe MMu
1ranslaLe a vlrLual address Lo a physlcal address
1ranslauon Lookaslde 8uer (1L8)
Lssenually a cache for Lhe MMu's vlrLual-Lo-physlcal Lranslauons Lable
noL needed for correcLness buL source of $%&'%()*'+ performance galn
13
Cu
1ranslauon
1able
MMu
Memory
3%.45'( /00.+$$
!"#$%&'(
/00.+$$
1L8
Memory Allocauon
14
Pow should we allocaLe memory Lo
processes?
!"#$%&'( *+,-.#
MMu
llxed aruuons
13
1
2
3
4
3
hyslcal Memory
8ase 8eglsLer
4's 8ase
vlrLual Address
CseL +
hyslcal memory ls broken up lnLo xed paruuons
Pardware requlremenLs: base reglsLer
hyslcal address = vlrLual address + base reglsLer
llxed aruuons
hyslcal memory ls broken up lnLo xed paruuons
Pardware requlremenLs: base reglsLer
hyslcal address = vlrLual address + base reglsLer
8ase reglsLer loaded by CS when lL swlLches Lo a process
Slze of each paruuon ls Lhe same and xed
Pow do we provlde proLecuon?
AdvanLages
Lasy Lo lmplemenL, fasL conLexL swlLch
roblems
lnLernal fragmenLauon: memory ln a paruuon noL used by a
process ls noL avallable Lo oLher processes
aruuon slze: one slze does noL L all (very large processes?)
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varlable aruuons
naLural exLenslon - physlcal memory ls broken up lnLo
varlable slzed paruuons
Pardware requlremenLs: base reglsLer and llmlL reglsLer
hyslcal address = vlrLual address + base reglsLer
Why do we need Lhe llmlL reglsLer? roLecuon
lf (physlcal address > base + llmlL) Lhen proLecuon faulL
17
varlable aruuons
18
1
2
3
hyslcal Memory
8ase 8eglsLer
4's 8ase
vlrLual Address
CseL
+
LlmlL 8eglsLer
3's 8ase
<
?es?
no?
roLecuon laulL
varlable aruuons
naLural exLenslon - physlcal memory ls broken up lnLo
varlable slzed paruuons
Pardware requlremenLs: base reglsLer and llmlL reglsLer
hyslcal address = vlrLual address + base reglsLer
Why do we need Lhe llmlL reglsLer? roLecuons
lf (physlcal address > base + llmlL) Lhen excepuon faulL
AdvanLages
no lnLernal fragmenLauon: allocaLe [usL enough for process
roblems
LxLernal fragmenLauon: [ob loadlng and unloadlng
produces empLy holes scauered LhroughouL memory
19
aglng
aglng solves Lhe exLernal fragmenLauon problem by uslng xed slzed
unlLs ln boLh physlcal and vlrLual memory
20
age 1
age 2
age 3
age 4
age 3
hyslcal Memory
age 1
age 2
age n
vlrLual Memory
.
.
.

user/rocess erspecuve
users (and processes) vlew memory as one conuguous
address space from 0 Lo n
vlrLual address space
ln reallLy, pages are scauered LhroughouL physlcal sLorage
1he mapplng ls lnvlslble Lo Lhe program
roLecuon ls provlded because a program cannoL reference
memory ouLslde of lLs vlrLual address space
1he address 0x1000" maps Lo dlerenL physlcal addresses ln dlerenL
processes
21
aglng
1ranslaung addresses
vlrLual address has Lwo parLs: vlrLual page number and oseL
vlrLual page number (vn) ls an lndex lnLo a page Lable
age Lable deLermlnes page frame number (ln)
hyslcal address ls ln::oseL
22
0x8AAul00u =
oseL vlrLual page number
0x8AAul 0x00u
1ranslauon
1able
page Lable
0x8AAul 0x900ul
physlcal page number
(page frame number)
vlrLual page number
vlrLual address
age Lookups
23
age 1
age 2
age 3
age n
hyslcal Memory
.
.
.

age frame CseL
hyslcal Address
age number CseL
vlrLual Address
age frame
age 1able
0x8AAul00u
0x8AAul 0xl00u
0xl00u 0x900ul
0x900ul00u
0xllllllll
0x00000000
aglng
1ranslaung addresses
vlrLual address has Lwo parLs: vlrLual page number and oseL
vlrLual page number (vn) ls an lndex lnLo a page Lable
age Lable deLermlnes page frame number (ln)
hyslcal address ls ln::oseL
age Lables
Map vlrLual page number (vn) Lo page frame number (ln)
vn ls Lhe lndex lnLo Lhe Lable LhaL deLermlnes ln
Cne page Lable enLry (1L) per page ln vlrLual address space
Cr, one 1L per vn
24
aglng Lxample
Memory address ls 32 blLs
ages are 4k
vn ls blLs ( vns), oseL ls blLs
vlrLual address ls 0x7468
vlrLual page ls , oseL ls _______
age Lable enLry conLalns 0x2
age frame base ls 0x2 << = _______
_____Lh vlrLual page ls address _______ (3
rd
physlcal page)
hyslcal address = _____ + _____ = ______
23
aglng Lxample
Memory address ls 32 blLs
ages are 4k
vn ls 20 blLs ( 1M vns), oseL ls 12 blLs
vlrLual address ls 0x7468
vlrLual page ls 0x7 , oseL ls _0x468__
age Lable enLry 0x7 conLalns 0x2
age frame base ls 0x2 << 12 blLs =__0x2000__
___7_Lh vlrLual page ls address 0x2000 (3
rd
physlcal page)
hyslcal address = _0x2000_ + _0x468_ = _0x2468_
26
nexL 1lme
8ead ChapLer 8.3-8.8
eerwlse quesuons due Lomorrow aL mldnlghL.
Check Web slLe for course announcemenLs
hup://www.cs.ucsd.edu/classes/su09/cse120
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