CUPL Tutorial
We will walk through the steps in creating a circuit implementation in a 22V10 chip using the Atmel/ Logical
Deices CUPL so!tware an" the Chip#aster $000 so!tware !or programming the chip%
To see more a&out the 2210' go here%
"eice%html
The "esign(
We will "esign an" construct a simple )&ouncing &all ) L*D circuit using onl+ a 2210 an" a L*D &ar,graph circuit%
The circuit will &ehae like the !ollowing(
clock
C 1 1 0 1 1 1 1 1
C 1 0 1 1 1 1 1 1
C 0 1 1 1 1 1 1 1
C 1 0 1 1 1 1 1 1
C 1 1 0 1 1 1 1 1
C 1 1 1 0 1 1 1 1
C 1 1 1 1 0 1 1 1
C 1 1 1 1 1 0 1 1
C 1 1 1 1 1 1 0 1
C 1 1 1 1 1 1 1 0
C 1 1 1 1 1 1 0 1
Thus' the circuit is essentiall+ a )one,hot)' or in this case' an actie,low )-ero,hot) counter with a latch resere" !or
recor"ing the current "irection o! the &all% We will construct the circuit using state,machines in the CUPL s+nta.%
To start' the CUPL so!tware shoul" &e installe" correctl+% Check here to make sure%
To start the CUPL so!tware package' t+pe #CUPL at the D/0 C( prompt in the CUPL "irector+%+ou shoul" see this
pop up(
an" then the menu shoul" !ollow in a secon" or a!ter pressing enter(
1aigation is accomplishe" &+ using the arrow ke+s on the ke+pa" to select the option on the #ain #enu%
Alternatiel+' the option can &e selecte" &+ pressing the ke+&oar" letter correspon"ing to the option letter in
&rackets%
2t is a goo" i"ea to take the time an" e.plore the "i!!erent menu options to get !amiliar with naigation% The !irst
thign to "o is select the "eice 3 Deice 0election4% Press 5D6 or select it using the arrow ke+s%At the ne.t prompt
choose the P22V10 "eice% 2t will then prompt !or the package% We want the D2P 3"ual in,line4 package%
7aing picke" the "eice' we will now create a new !ile !or the &ouncing L*D "eice% At the main menu ' choose
<*6"it "esign !ile to start work on a new !ile%At the prompt' t+pe in &ounce%pl" as the new !ile name an" then press
*nter% 8ou shoul" now &e in the #0,D/0 *D2T program%
The !irst thing to "o is enter the hea"er in!ormation The hea"er in!ormation is use" to keep track o! the reisions an"
"eice selection% The !ormat is(
1ame 9ounce:
Partno 01:
Date 1/1$/;<:
=e 01:
Designer >oe Programmer:
Compan+ U% Penn:
Assem&l+ 1one:
Location 1one:
Deice P22V10:
This in!ormation is inclu"e" at the &eginning o! eer+ %pl" !ile%
The ne.t thing to "o is asign the pins to speci!ic input an" output aria&les% To start with' we will asign the P2210
the !ollowing(
Pin Declarations
/??2nputs??/
Pin 1 @ CLA:
Pin 2 @ reset:
/??/utputs??/
Pin 1B @ outC:
Pin 1$ @ out2:
Pin 1< @ out1:
Pin 1D @ out0:
Pin 1; @ "ir:
The ne.t part !or the "esign is to "eclare the states using define statements that hae the same usage as in
programming languages such as C% This is important !or eas+ e"iting an" rea"a&ilit+ o! the co"e% 2! use" correctl+'
define statements can relegate "esign changes to e"iting o! the hea"er statements%
The s+nta. !or a define statement is the !ollowing(
E"e!ine replacementvalue value
We will use the "e!ine statement a!ter the Pin "eclarations
ED*F21* 00 G&G1111
ED*F21* 01 G&G1110
ED*F21* 02 G&G1101
ED*F21* 0C G&G1011
ED*F21* 0H G&G0111
thus' when the !ile is run through the precompiler' the 0. alues will &e replace" with the &inar+ alues%
The ne.t thing to "o is "eclare the output F2*LD% Look here to see more a&out the s+nta.%
F2*LD count@IoutC%%0J:
count%A=@ reset:
count%0P@ G&G1111:
the %A= an" %0P a!ter count in the two !ollowing lines are known as e.tensions% *.tensions control speci!ic inputs to
the t+pe o! !lip,!lop &eing use" in the circuit%
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
CUPL Tutorial( CUPL 0+nta.
1um&er 9ases
1um&er 9ase Decimal
G&G0 9inar+ 0
G9G1101 9inar+ 1C
G/G$$C /ctal HCB
GDG;2 Decimal ;2
GhG9A 7e.a"ecimal 1D$
G/GIC00%%H<<J /ctal3=ange4 1;2%%C1H
G7G<FKK
7e.a"ecimal3=ang
e4
C2B12%%C2<$<
List 1otation*.amples
F2*LD DATA @ ID<%%D0J:
F2*LD Assert @ I2/W' 2/=' AL*J:
Logical /perators
/perator *.amples Description Prece"ence
L LA 1/T 1
M A M 9 A1D 2
N A N 9 /= C
E A E 9 K/= H
Arithmatic Operators3use" in E=*P*AT an" E#AC=/4
/perator *.amples Description Prece"ance
?? 2??C
*.ponentiatio
n
1
? 2?1 #ultiplication2
/ H/2 Diision 2
O ;OD #o"ulus 2
P 2PH A""ition C
, H, 1 0u&traction C
VariableExtensions
*.tensions are use" to "eclare speci!ic inputso! a !lip,!lop t+pe "eice in the chip &eing use"% For e.ample' agroup
o! D !lip,!lops groupe" into a register can hae theiras+nchronous reset 3%A=4 treate" in the !ollowing wa+(
F2*LDregister @ I"ata<%%"ata0J: register%A=@ reset:
*.tension 0i"e Use" Description
%AP L
As+nchronous
preset o! !,!
%A= L
As+nchronous reset
o! !,!
%AP#UK L
As+nchronous
preset multiple.er
selection
%A=#UK L
As+nchronous reset
multiple.er
selection
%98P
%CA
%C*
%CA
%CA#UK
%D
%DF9
%DQ
%2#UK
%21T
%2/
%2/A=
%2/AP
%2/CA
%2/D
%2/L
%2/0P
%2/0=
%>
%A
%L
%L*
%L*#UK
%LF9
%LQ
%/90
%/* L
Prgramma&le
/utput *na&le
%/*#UK
%P= L
Programma&le
=eloa"
%=
%0
%0P L
0+nchronous preset
o! !lip,!lop
%0= L
0+nchronous reset
o! !lip,!lop
%T
%T*C
Logic Equations
Set Operations
State Machines
0*QU*1C* ' 0*QU*1C*D' 0*QU*1C*>A' 0*QU*1C*=0' 0*QU*1C*T, !orcethe state registers in the state
machine to &e generate" as"e!ault' D' >,A' 0,=' an" T !lip,!lops% 9e care!ul to check whatis aaila&le in the "eice
&eing use"%
Example:
0*QU*1C* statevariables{
P=*0*1T state_n0
2F 3con"ition14 1*KT stateRn1:
2F 3con"ition24 1*KT stateRn2:
D*FAULT 1*KT stateRn0:
%
%
%
P=*0*1T stateRnn
2F %%%:
S
CUPL Tutorial !or ** CC0
Architecture o! the 2210
The 2210 "eice is a programma&le logic "eice "esigne" toimplement custom logic !unctions similar in
comple.it+ to the <Hseries o! logic chips% 2t has the a"antage o! "elieringcustomi-e" !unctions that might &e
"i!!icult to implement or takemultiple chips using <H series chips% T+pical applications !orthis are state machines
use" !or things such as "irect memor+access controllers in PCs%
The 2210 consists o! twele inputs connecte" to a regularsum,o!,pro"ucts arra+ an" ten output logic macrocells%
Thesum,o!,pro"ucts arra+ has programma&le interconnections that"etermine the pro"uct terms connecte" to the or,
gate% *!!icientuse o! these sum,o!,pro"ucts gates reTuires implementing!unctions in the same !orm an" minimi-ing
through the use o!metho"s such as Aarnaugh maps: there are a limite" num&er o!inputs to these sum,o!,pro"ucts
terms% The or,gates in each logicmacrocell are connecte" either to a D !lip,!lop in registere"!orm or "irectl+ to the
output &u!!ers in com&inatorial !orm%Fee"&ack is implemente" through the connection o! the D !lip,!lopoutput to a
column in the pro"uct,term arra+% /ther !eaturesinclu"e(
A single pro"uct term to control the output &u!!er
*er+ output has at least D pro"uct terms aaila&le
A single pro"uct term is aaila&le to generate a glo&al'
as+nchronous reset
A single pro"uct term is aaila&le to generate a preset signal
for a Troubleshooting
Q% When 2 compile or simulate' it tells me that there were C02# errors &ut then "oesnGt tell me what the+ are%
A% Look in the 0/ !ile% 2t will tell +ou what the error is%
Q% When 2 am compiling' 2 get C02# errors' &ut 2Gm not tr+ing to simulate it +et%
A% Turn o!! simulation in the Compiler /ptions menu%
Q% 2t tells me 2 hae too man+ pro"uct terms when 2 compile it% 1ow what "o 2 "o
A% Look in the D/C !ile where it tells how man+ are aaila&le an" how man+ are use"% 1ow that +ou know this' +ou
can(
1% A"Uust which pin +ou are using to get more aaila&le pro"uct terms 3this is part "epen"ent4%
2% Change the minimi-ation options%
C% Change +our logic so it uses less pro"uct terms 3"e!initel+ the most "i!!icult4%
Q% When 2 compile 2 get an error similar to( )Una&le to open =U1F2T%EEE)%
A% This generall+ in"icates that CUPL has run out o! memor+ 3use" it up4 so +ou nee" to e.it an" restart CUPL%
Selecting Simulation options
This allows +ou to speci!+ options "irectl+ !or the simulations% Un"er the options menu' choose the )0imulator
/ptions) item% Listing File( Venerates a simulator listing !ile with the input an" output alues !or each aria&le are
liste"% *rror messages are liste" !ollowing each ector' with the signal name in error "ispla+e"% 30/ !ile4 Append
Vectors( Appen"s the structure" test ectors generate" &+ the simulation onto the e.isting >*D*C "ownloa" !ile%
This shoul" allow +ou to ph+sicall+ test the "eice with the programmer% ispla! "esults( Displa+s the contents o!
the listing !ile in a win"ow% An 0/ !ile is necessar+ !or this to work%
Standard #ompilation and Simulation $rocedure
1% /pen a CUPL !ile 3PLD !ile4 or create a new one%
2% #ake sure that +our "eice is correctl+ selecte" 3menu' or in the program hea"er4
C% 2n the Compiler options menu' check that the correct logic minimi-ation is selecte"% 7ae eer+thing
unchecke" in the #iscellaneous section% 7ae the >*D*C' eTuations' a&solute' an" list output !ile options
selecte"%
H% 0elect Deice 0peci!ic Compile un"er the =un menu%
B% 1ow "e&ug all o! +our errors as liste" in L0T !ile an" D/C !ile%
$% To 0imulate' open or create the simulation !ile 302 !ile4%
<% 2n the 0imulator /ptions menu' make sure that the Listing File an" Displa+ =esults /ptions are selecte"%
D% 0elect Deice 0peci!ic 0imulate un"er the =un menu%
;% 2! +ou get an+ simulation errors' check in the 0/ !ile% /therwise' look at the wae!orms in the new
win"ows an" see i! the+ are correct% Press FH to close this win"ow or WXY to get more help%
10%
http(//www%eca"%com/cupl/"ocs/tutorial%htm
