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Computer System Architecture Lab Manual

This document outlines the detailed syllabus for a 50-hour Computer System Architecture and Digital System Design Lab course. The term work will consist of a record of experiments including simulating and verifying logic gates and various adders, decoders, multiplexers, and encoders. Students will also design and simulate counters, registers, sequence detectors, multipliers, arithmetic logic units, and RAM with read and write operations. Additional experiments will cover stack and queue implementation and other topics from the subject code.

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deepakdewangan27
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609 views

Computer System Architecture Lab Manual

This document outlines the detailed syllabus for a 50-hour Computer System Architecture and Digital System Design Lab course. The term work will consist of a record of experiments including simulating and verifying logic gates and various adders, decoders, multiplexers, and encoders. Students will also design and simulate counters, registers, sequence detectors, multipliers, arithmetic logic units, and RAM with read and write operations. Additional experiments will cover stack and queue implementation and other topics from the subject code.

Uploaded by

deepakdewangan27
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Subject Code: 3215010 Computer System Architecture and Digital System Design Lab

Total No. of Classes: 50 Hours


Detailed Syllabus
Term work: Term work shall consist of record of the experiments, based on the following:
1. Simulation and Verification of Logic Gates.
2. Design and Simulation of
(a) Half adder (b) Full adder (c) Serial Binary adder
(d) Carry Look Ahead adder (e) Ripple Carry adder
3. Simulation and Verification of
(a) Decoder (b) Mux (c) Encoder
4. Modeling of Flip-Flops
(a) SR Flip-Flops (b) D Flip-Flops
(c) JK Flip-Flops (d) T Flip-Flops
5. Design and Simulation of Counters
(a) Ring Counters (b) Johnson Counters
(c) Up-Down Counters (d) Ripple Counters (Asynchronous)
6. Design of a N- bit Register
(a) Serial-in Serial-out (b) Serial in Parallel out
(c) Parallel in Serial out (d) Parallel in Parallel out
7. Design of Sequence detector.
8. 4-Bit Multiplier (Array)
9. Design of ALU.
10. RAM (Read and Write Operations)
11. Stack and Queue Implementation.

More experiments must be there with reference to the contents of subject code 321502

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