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Stop Watch Coding (VHDL)

This document describes a stop watch design implemented on a CoolRunner-II CPLD. It includes the following key components: 1. A state machine (STMACH) that controls the operation of the stop watch in response to start/stop and reset inputs. 2. A tenths counter (TENTHS) that counts the tenths of a second. 3. A CNT60 module that counts from 0 to 59 to track the seconds and tens of seconds. 4. Hexadecimal to 7-segment decoders (HEX2LED) that convert the numeric outputs to 7-segment LED display formats for the ones and tens digits. The design outputs include the tens, ones,

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698 views

Stop Watch Coding (VHDL)

This document describes a stop watch design implemented on a CoolRunner-II CPLD. It includes the following key components: 1. A state machine (STMACH) that controls the operation of the stop watch in response to start/stop and reset inputs. 2. A tenths counter (TENTHS) that counts the tenths of a second. 3. A CNT60 module that counts from 0 to 59 to track the seconds and tens of seconds. 4. Hexadecimal to 7-segment decoders (HEX2LED) that convert the numeric outputs to 7-segment LED display formats for the ones and tens digits. The design outputs include the tens, ones,

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Anonymous ZCb9xz
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© © All Rights Reserved
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STOP WATCH

DEVICE:PRODUCT CATEGORY- ALL


FAMILY- COOLRUNNER2CPLDS
DEVICE- XC2C128
PACKAGE-TQ144
SPEED- (-6)

MACHINE(STMCHINE):library IEEE;
use IEEE.std_logic_1164.all;
entity stmchine is
port(CLK, RESET, STRTSTOP : in STD_LOGIC;
CLKEN, RST : out STD_LOGIC
);
end stmchine;
architecture inside of stmchine is
type stmchine_state is (clear, zero, start, counting, stop, stopped);
-- attribute syn_encoding : string;
-- attribute syn_encoding of stmchine_state : type is "binary";
signal current_state, next_state : stmchine_state;
-- attribute state_machine : boolean;
-- attribute state_machine of current_state : signal is true;
begin
process(STRTSTOP, current_state)
begin
-- Assign defaults, so as not set them in every state
CLKEN <= '0';
RST <= '0';
case current_state is
when clear => next_state <= zero;
RST <= '1';

when zero =>


if (STRTSTOP = '0') then
next_state <= zero;
elsif (STRTSTOP = '1') then
next_state <= start;
end if;
when start =>
if (STRTSTOP = '0') then
next_state <= counting;
elsif(STRTSTOP = '1') then
next_state <= start;
end if;
when counting =>
if (STRTSTOP = '0') then
next_state <= counting;
elsif (STRTSTOP = '1') then
next_state <= stop;
end if;
CLKEN <= '1';
when stop =>
if (STRTSTOP = '0') then
next_state <= stopped;
elsif (STRTSTOP = '1') then
next_state <= stop;
end if;
when stopped =>
if (STRTSTOP = '0') then
next_state <= stopped;
elsif (STRTSTOP = '1') then
next_state <= start;
end if;
when others => null;
end case;
end process;
process(RESET, CLK)
begin
if (RESET = '1') then
current_state <= clear;
elsif (CLK'event) then

current_state <= next_state;


end if;
end process;
end inside;

XCOUNTER(TENTHS):library IEEE;
use IEEE.std_logic_1164.all;
entity tenths is
port(
CLK_EN: IN std_logic;
CLOCK: IN std_logic;
ASYNC_CTRL: IN std_logic;
Q_OUT: OUT std_logic_vector(9 DOWNTO 0);
TERM_CNT: OUT std_logic
);
end tenths;
architecture inside of tenths is
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
attribute enum_encoding: string;
attribute enum_encoding of state_type: type is "0000000001 0000000010
0000000100 0000001000 0000010000 0000100000 0001000000
0010000000 0100000000 1000000000";
signal cs: state_type;
signal ns: state_type;
begin
process(CLK_EN,CLOCK,ASYNC_CTRL)
begin

if(ASYNC_CTRL='1') then
cs <= s0;
elsif(CLK_EN='1') then
if(CLOCK'event) then
cs <= ns;
end if;
end if;
end process;
process(cs)
begin
case cs is
when s0=>
ns<=s1;
Q_OUT<="0000000001";
when s1=>
ns<=s2;
Q_OUT<="0000000010";
when s2=>
ns<=s3;
Q_OUT<="0000000100";
when s3=>
ns<=s4;
Q_OUT<="0000001000";
when s4=>
ns<=s5;
Q_OUT<="0000010000";
when s5=>
ns<=s6;
Q_OUT<="0000100000";
when s6=>
ns<=s7;
Q_OUT<="0001000000";
when s7=>
ns<=s8;
Q_OUT<="0010000000";
when s8=>
ns<=s9;
Q_OUT<="0100000000";
when s9=>

ns<=s0;
Q_OUT<="1000000000";
end case;
end process;
process(cs)
begin
if(cs=s9) then
TERM_CNT<='1';
else
TERM_CNT<='0';
end if;
end process;
end inside;

SIXTY(CNT60):library ieee;
use ieee.std_logic_1164.all;
entity CNT60 is
port (CE, CLK, CLR : in std_logic;
LSBSEC, MSBSEC : out std_logic_vector(3 downto 0));
end CNT60;
architecture XILINX of CNT60 is
component SMALLCNTR
port (CE, CLK, CLR : in std_logic;
QOUT : out std_logic_vector(3 downto 0));
end component;
signal LSBOUT, MSBOUT : std_logic_vector(3 downto 0);
signal MSBCE, LSBTC, MSBCLR, MSBTC : std_logic;
begin

LSBCOUNT : SMALLCNTR
port map(CE => CE, CLK => CLK, CLR => CLR, QOUT => LSBOUT);
MSBCOUNT : SMALLCNTR
port map(CE => MSBCE, CLK => CLK, CLR => MSBCLR, QOUT =>
MSBOUT);
LSBTC <= '1' when (LSBOUT = "1001") else '0';
MSBTC <= '1' when (MSBOUT = "0110") else '0';
MSBCE <= CE and LSBTC;
MSBCLR <= CLR or MSBTC;
LSBSEC <= LSBOUT;
MSBSEC <= MSBOUT;
end XILINX;

(LSB COUNT)SMALLCNTR:library ieee;


use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SMALLCNTR is
port (CE, CLK, CLR : in std_logic;
qout : out std_logic_vector(3 downto 0));
end SMALLCNTR;
architecture XILINX of SMALLCNTR is
signal QOUTSIG : std_logic_vector(3 downto 0);
begin
process(CE, CLK, CLR)
begin
if (CLR = '1') then
QOUTSIG <= "0000";

elsif (CLK'event) then


if (CE = '1') then
if (QOUTSIG = "1001") then
QOUTSIG <= "0000";
else
QOUTSIG <= QOUTSIG + "0001";
end if;
end if;
end if;
end process;
QOUT <= QOUTSIG;
end XILINX;

MSB COUNT(SMALL CNTR):library ieee;


use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SMALLCNTR is
port (CE, CLK, CLR : in std_logic;
qout : out std_logic_vector(3 downto 0));
end SMALLCNTR;
architecture XILINX of SMALLCNTR is
signal QOUTSIG : std_logic_vector(3 downto 0);
begin
process(CE, CLK, CLR)
begin
if (CLR = '1') then
QOUTSIG <= "0000";
elsif (CLK'event) then
if (CE = '1') then

if (QOUTSIG = "1001") then


QOUTSIG <= "0000";
else
QOUTSIG <= QOUTSIG + "0001";
end if;
end if;
end if;
end process;
QOUT <= QOUTSIG;
end XILINX;

HEX2LED:(LSB LED)library IEEE;


use IEEE.std_logic_1164.all;
entity hex2led is
port (HEX : in STD_LOGIC_VECTOR(3 downto 0);
LED : out STD_LOGIC_VECTOR(6 downto 0));
end hex2led;
architecture XILINX of hex2led is
begin
process(HEX)
begin
case HEX is
when "0001" => LED <= "1111001";
when "0010" => LED <= "0100100";
when "0011" => LED <= "0110000";
when "0100" => LED <= "0011001";
when "0101" => LED <= "0010010";
when "0110" => LED <= "0000010";
when "0111" => LED <= "1111000";

when "1000" => LED <= "0000000";


when "1001" => LED <= "0010000";
when "1010" => LED <= "0001000";
when "1011" => LED <= "0000011";
when "1100" => LED <= "1000110";
when "1101" => LED <= "0100001";
when "1110" => LED <= "0000110";
when "1111" => LED <= "0001110";
when others => LED <= "1000000";
end case;
end process;
end XILINX;

(MSB LED)library IEEE;


use IEEE.std_logic_1164.all;
entity hex2led is
port (HEX : in STD_LOGIC_VECTOR(3 downto 0);
LED : out STD_LOGIC_VECTOR(6 downto 0));
end hex2led;
architecture XILINX of hex2led is
begin
process(HEX)
begin
case HEX is
when "0001" => LED <= "1111001";
when "0010" => LED <= "0100100";
when "0011" => LED <= "0110000";
when "0100" => LED <= "0011001";
when "0101" => LED <= "0010010";
when "0110" => LED <= "0000010";
when "0111" => LED <= "1111000";
when "1000" => LED <= "0000000";

when "1001" => LED <= "0010000";


when "1010" => LED <= "0001000";
when "1011" => LED <= "0000011";
when "1100" => LED <= "1000110";
when "1101" => LED <= "0100001";
when "1110" => LED <= "0000110";
when "1111" => LED <= "0001110";
when others => LED <= "1000000";
end case;
end process;
end XILINX;

MAIN PROJECT

library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity watch is
port (RESET, CDRST,STRTSTOP : in STD_LOGIC;
CLK : in STD_LOGIC;
TENSOUT, ONESOUT : out STD_LOGIC_VECTOR(6 downto 0);
TENTHSOUT : out STD_LOGIC_VECTOR(9 downto 0));
end watch;
architecture XILINX of watch is
component CLK_DIV16R port (

CLKIN : in std_logic;
CDRST : in std_logic;
CLKDV : out std_logic
);
end component;
component stmchine
port (CLK, RESET, STRTSTOP : in STD_LOGIC;
CLKEN, RST : out STD_LOGIC);
end component;
component tenths
port (CLOCK, CLK_EN, ASYNC_CTRL : in STD_LOGIC;
TERM_CNT : out STD_LOGIC;
Q_OUT : out STD_LOGIC_VECTOR(9 downto 0));
end component;
component cnt60
port (CE, CLK, CLR : in STD_LOGIC;
LSBSEC, MSBSEC : out STD_LOGIC_VECTOR(3 downto 0));
end component;
component hex2led
port (HEX : in STD_LOGIC_VECTOR(3 downto 0);
LED : out STD_LOGIC_VECTOR(6 downto 0));
end component;
signal clkint, clkenable : STD_LOGIC;
signal strtstopinv, rstint, xtermcnt, cnt60enable : STD_LOGIC;
signal xcountout : STD_LOGIC_VECTOR(9 downto 0);
signal lsbcnt, msbcnt : STD_LOGIC_VECTOR(3 downto 0);
begin
MACHINE : stmchine
port map(CLK => clkint, RESET => RESET, STRTSTOP => strtstopinv,
CLKEN => clkenable, RST => rstint);
XCOUNTER : tenths

port map(CLOCK => clkint, CLK_EN => clkenable, ASYNC_CTRL =>


rstint,
TERM_CNT => xtermcnt, Q_OUT => xcountout);
SIXTY : cnt60
port map(CE => cnt60enable, CLK => clkint, CLR => rstint,
LSBSEC => lsbcnt, MSBSEC => msbcnt);
LSBLED : hex2led
port map(HEX => lsbcnt, LED => ONESOUT);
MSBLED : hex2led
port map( HEX => msbcnt, LED => TENSOUT);
U1 : CLK_DIV16R port map (CLKIN => CLK,
CDRST => CDRST,
CLKDV => clkint);
cnt60enable <= xtermcnt and clkenable;
TENTHSOUT <= not(xcountout);
strtstopinv <= not(STRTSTOP);
end XILINX;

RTL SCHEMATIC:CHIP DIAGRAM-

SCHEMATIC DIAGRAM-

HINTS:::--WATCHVHD is a top level VHDL type project of a Stop Watch.


DESIGN TYPE:
Foundation ISE (chip CoolRunner-II)
CONTROLS
Inputs:
* CLK -System clock for the Watch design.
* STRTSTOP -Starts and stops the stoopwatch. This is an active-low signal
which acts like the start/stop button on a runner's stop-watch.
* RESET -Resets the stopwatch to 00.0 after it has been stopped.
Outputs:
* TENSOUT[6:0] -7-bit bus which represents the Tens digit of the
stopwatch
value. This bus is in 7-segment display format to be viewable
on the 7-segment LED display.
* ONESOUT[6:0] -similar to TENSOUT bus above, but represents the Ones
digit
of the stopwatch value.
* TENTHSOUT[9:0] -10-bit bus which represents the Tenths digit of the
stopwatch
value. This bus is one-hot encoded.
DESCRIPTION:
* STMACH -State Machine macro. This module uses the VSS
StateCAD Editor to enter and implement the state machine.
* CNT60 -VHDL-based module which counts from 0 to 59, decimal. This
macro
has two 4-bit outputs, which represent the 'ones' and 'tens' digits of
the decimal values, respectively.
* TENTHS -A 10-bit counter. This macro outputs the
'tenths' digit of the watch value.

* HEX2LED -HDL-based macro. This macro decodes the ones and tens
digit values
from hexadecimal to 7-segment display format.
SIMULATION:
Requires the following simulation libraries:
Unisims
Simprims
Behavioural and RTL Simulation done using Testbench Waveform
file(watch_tb.tbw).
---------------------------------------------------------------------------------------------------

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