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Simulation

The document describes the timing of sampling two analog to digital converters (ADC1 and ADC2) with a resolution of 8 bits each. Each ADC sampling takes 3 cycles, with a required delay of 6 cycles between sampling each ADC. The conversion phase to generate the digital output takes 8 cycles. The timing diagram shows the sampling of each ADC alternating with the required delay between, along with the converted digital data output.

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M Faizan Farooq
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© © All Rights Reserved
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14 views

Simulation

The document describes the timing of sampling two analog to digital converters (ADC1 and ADC2) with a resolution of 8 bits each. Each ADC sampling takes 3 cycles, with a required delay of 6 cycles between sampling each ADC. The conversion phase to generate the digital output takes 8 cycles. The timing diagram shows the sampling of each ADC alternating with the required delay between, along with the converted digital data output.

Uploaded by

M Faizan Farooq
Copyright
© © All Rights Reserved
Available Formats
Download as XLS, PDF, TXT or read online on Scribd
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ADC1

ADC2
CH12data A A A A A A
1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3
Legend
Idle Time (due to delay : 6cycles must separate sampling ADC1 and Sampling ADC2)
Sampling time : 3 cycles
Delay between sampling of 2 ADC : 6 cycles
Convertion phase : 8 cycles (resolution=8bit ==> Conversion time = 8 cycles)
A Converted data availble
A A A
4 5 6 1 2 3 4 5 6 1 2 3 4 5 6
Idle Time (due to delay : 6cycles must separate sampling ADC1 and Sampling ADC2)

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