Modeling and Behavioral Simulation of A High-Speed Phase Locked Loop For Frequency Synthesis

This document is a submission for an M.Tech course in signal processing. It summarizes a research paper on modeling and simulating a high-speed phase locked loop for frequency synthesis. The submission was authored by Hemant Tulsani and guided by Dr. R.K. Sharma. The summarized research paper was written by K. Kalita, J. Handique, and T. Bezboruah, and was published in the IET Signal Processing Journal in 2012.

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Modeling and Behavioral Simulation of A High-Speed Phase Locked Loop For Frequency Synthesis

Uploaded by

Hemant Tulsani

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Modeling and behavioral

simulation of a high-speed
phase locked loop for
frequency synthesis

Submitted By:
Name Hemant Tulsani
Course M.Tech. (Signal Processing)
Enroll. No. 00110100512

Under The Guidance Of:

Dr. R.K. Sharma

Associate Professor

AIACTR

A Paper By: K. Kalita [1] J. Handique [1] T. Bezboruah [1,2]
[1] Department of Electronics & Communication Technology, Gauhati University, Guwahati
781014, Assam, India
[2] Multidisciplinary Laboratory, The Abdus Salam International Centre for Theoretical Physics
(ICTP), Strada Costiera 11, I 34151, Trieste, Italy

Published in
IET Signal Processing Journal,
2012, Vol. 6, Issue 3

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