2002 Fairchild Semiconductor Corporation DS005661 www.fairchildsemi.

com
November 1983
Revised March 2002
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CD4016BC
Quad Bilateral Switch
General Description
The CD4016BC is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin-for-pin compatible with CD4066BC.
Features
I Wide supply voltage range: 3V to 15V
I Wide range of digital and analog switching: 7.5 V
PEAK
I ON Resistance for 15V operation: 400 (typ)
I Matched ON Resistance over 15V signal input:
R
ON
= 10 (typ)
I High degree of linearity:
0.4% distortion (typ)
@ f
IS
= 1 kHz, V
IS
= 5 V
p-p
,
V
DD
V
SS
= 10V, R
L
= 10 k
I Extremely low OFF switch leakage:
0.1 nA (typ.)
@ V
DD
V
SS
= 10V
T
A
= 25C
I Extremely high control input impedance: 10
12
(typ)
I Low crosstalk between switches:
50 dB (typ.)
@ f
IS
= 0.9 MHz, R
L
= 1 k
I Frequency response, switch ON: 40 MHz (typ)
Applications
Analog signal switching/multiplexing
Signal gating
Squelch control
Chopper
Modulator/Demodulator
Commutating switch
Digital signal switching/multiplexing
CMOS logic implementation
Analog-to-digital/digital-to-analog conversion
Digital control of frequency, impedance, phase, and
analog-signal gain

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the letter suffix X to the ordering code.
Connection Diagram Schematic Diagram

Order Number Package Number Package Description
CD4016BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4016BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of Recom-
mended Operating Conditions and Electrical Characteristics provide con-
ditions for actual device operation.
Note 2: V
SS
= 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
Note 3: If the switch input is held at V
DD
, V
IHC
is the control input level that will cause the switch output to meet the standard B series V
OH
and I
OH
output
levels. If the analog switch input is connected to V
SS
, V
IHC
is the control input level which allows the switch to sink standard B series |I
OH
|, HIGH level
current, and still maintain a V
OL
B series. These currents are shown in Table 1.
V
DD
Supply Voltage 0.5V to +18V
V
IN
Input Voltage 0.5V to V
DD
+ 0.5V
T
S
Storage Temperature Range 65C to + 150C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature
(Soldering, 10 seconds) 260C
V
DD
Supply Voltage 3V to 15V
V
IN
Input Voltage 0V to V
DD
T
A
Operating Temperature Range 55C to +125C
Symbol Parameter Conditions
55C 25C +125C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device V
DD
= 5V, V
IN
= V
DD
or V
SS
0.25 0.01 0.25 7.5 A
Current V
DD
= 10V, V
IN
= V
DD
or V
SS
0.5 0.01 0.5 15 A
V
DD
= 15V, V
IN
= V
DD
or V
SS
1.0 0.01 1.0 30 A
Signal Inputs and Outputs
R
ON
ON Resistance R
L
= 10k to (V
DD
V
SS
)/2
V
C
= V
DD
, V
IS
= V
SS
or V
DD
V
DD
= 10V 600 250 660 960
V
DD
= 15V 360 200 400 600
R
L
= 10k to (V
DD
V
SS
)/2
V
C
= V
DD
V
DD
= 10V, V
IS
= 4.75 to 5.25V 1870 850 2000 2600
V
DD
= 15V, V
IS
= 7.25 to 7.75V 775 400 850 1230
R
ON
ON Resistance R
L
= 10k to (V
DD
V
SS
)/2
Between any 2 of V
C
= V
DD
, V
IS
= V
SS
to V
DD
4 Switches V
DD
= 10V 15
(In Same Package) V
DD
= 15V 10
I
IS
Input or Output V
C
= 0, V
DD
= 15V 50 0.1 50 500 nA
Leakage V
IS
= 0V or 15V,
Switch OFF V
OS
= 15V or 0V
Control Inputs
V
ILC
LOW Level Input V
IS
= V
SS
and V
DD
Voltage V
OS
= V
DD
and V
SS
I
IS
= 10 A
V
DD
= 5V 0.9 0.7 0.5 V
V
DD
= 10V 0.9 0.7 0.5 V
V
DD
= 15V 0.9 0.7 0.5 V
V
IHC
HIGH Level Input V
DD
= 5V 3.5 3.5 3.5 V
Voltage V
DD
= 10V 7.0 7.0 7.0 V
V
DD
= 15V 11.0 11.0 11.0 V
(Note 3) and Table 1
I
IN
Input Current V
CC
V
SS
= 15V 0.1 10
5
0.1 1.0 A
V
DD
V
IS
V
SS
V
DD
V
C
V
SS
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AC Electrical Characteristics (Note 4)
T
A
= 25C, t
r
= t
f
= 20 ns and V
SS
= 0V unless otherwise specified
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: These devices should not be connected to circuits with the power ON.
Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in C
L
wherever it is
specified.
Note 7: V
IS
is the voltage at the in/out pin and V
OS
is the voltage at the out/in pin. V
C
is the voltage at the control input.
Symbol Parameter Conditions Min Typ Max Units
t
PHL
, t
PLH
Propagation Delay Time V
C
= V
DD
, C
L
= 50 pF, (Figure 1)
Signal Input to Signal Output R
L
= 200k
V
DD
= 5V 58 100 ns
V
DD
= 10V 27 50 ns
V
DD
= 15V 20 40 ns
t
PZH
, t
PZL
Propagation Delay Time R
L
= 1.0 k, C
L
= 50 pF, (Figure 2, Figure 3)
Control Input to Signal V
DD
= 5V 20 50 ns
Output HIGH Impedance to V
DD
= 10V 18 40 ns
Logical Level V
DD
= 15V 17 35 ns
t
PHZ
, t
PLZ
Propagation Delay Time R
L
= 1.0 k, C
L
= 50 pF, (Figure 2, Figure 3)
Control Input to Signal V
DD
= 5V 15 40 ns
Output Logical Level to V
DD
= 10V 11 25 ns
HIGH Impedance V
DD
= 15V 10 22 ns
Sine Wave Distortion V
C
= V
DD
= 5V, V
SS
= 5 0.4 %
R
L
= 10 k, V
IS
= 5 V
P-P
, f = 1 kHz,
(Figure 4)
Frequency Response Switch V
C
= V
DD
= 5V, V
SS
= 5V, 40 MHz
ON (Frequency at 3 dB) R
L
= 1 k, V
IS
= 5 V
P-P
,
20 Log
10
V
OS
/V
OS
(1 kHz) dB,
(Figure 4)
Feedthrough Switch OFF V
DD
= 5V, V
C
= V
SS
= 5V, 1.25 MHz
(Frequency at 50 dB) R
L
= 1 k, V
IS
= 5 V
P-P
,
20 Log
10
(V
OS
/V
IS
) = 50 dB,
(Figure 4)
Crosstalk Between Any Two V
DD
= V
C(A)
= 5V; V
SS
= V
C(B)
= 5V, 0.9 MHz
Switches (Frequency at 50 dB) R
L
= 1 kV
IS(A)
= 5 V
P-P
,
20 Log
10
(V
OS(B)
/V
OS(A)
) = 50 dB,
(Figure 5)
Crosstalk; Control Input to V
DD
= 10V, R
L
= 10 k 150 mV
P-P
Signal Output R
IN
= 1 k, V
CC
= 10V Square Wave,
C
L
= 50 pF (Figure 6)
Maximum Control Input R
L
= 1 k, C
L
= 50 pF, (Figure 7)
V
OS(f)
= V
OS
(1 kHz)
V
DD
= 5V 6.5 MHz
V
DD
= 10V 8.0 MHz
V
DD
= 15V 9.0 MHz
C
IS
Signal Input Capacitance 4 pF
C
OS
Signal Output Capacitance V
DD
= 10V 4 pF
C
IOS
Feedthrough Capacitance V
C
= 0V 0.2 pF
C
IN
Control Input Capacitance 5 7.5 pF
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AC Test Circuits and Switching Time Waveforms
FIGURE 1. t
PLH
, t
PLH
Propagation Delay Time Control to Signal Output
FIGURE 2. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
FIGURE 3. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
V
C
= V
DD
for distortion and frequency response tests
V
C
= V
SS
for feedthrough test
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
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AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 5. Crosstalk Between Any Two Switches
FIGURE 6. Crosstalk Control to Input Signal Output
FIGURE 7. Maximum Control Input Frequency
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TABLE 1. CD4016B Switch Test Conditions for V
IHC
Typical Performance Characteristics
ON Resistance vs.
Signal Voltage T
A
= 25C
ON Resistance Temperature Variation
for V
DD
V
SS
= 10V
ON Resistance Temperature Variation
for V
DD
V
SS
= 15V
Temperature Switch Input Switch Output
Range V
DD
V
IS
I
IS
(mA) V
OS
(V)
40C 25C +85C Min Max
COMMERCIAL
5 0 0.2 0.16 0.12 0.4
5 5 0.2 0.16 0.12 4.6
10 0 0.5 0.4 0.3 0.5
10 10 0.5 0.4 0.3 9.5
15 0 1.4 1.2 1.0 1.5
15 15 1.4 1.2 1.0 13.5
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Typical Applications
4 Input Multiplexer
Sample/Hold Amplifier
Special Considerations
The CD4016B is composed of 4, two-transistor analog
switches. These switches do not have any linearization or
compensation circuitry for R
ON
as do the CD4066B's.
Because of this, the special operating considerations for
the CD4066B do not apply to the CD4016B, but at low sup-
ply voltages, 5V, the CD4016B's On Resistance becomes
non-linear. It is recommended that at 5V, voltages on the
in/out pins be maintained within about 1V of either V
DD
or
V
SS
; and that at 3V the voltages on the in/out pins should
be at V
DD
or V
SS
for reliable operation.
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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