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EEP308 Computer Architecture Project Proposal: FIFO (First in First Out Queue) Control Logic

The document proposes a project to simulate a FIFO queue using assembly language and implement it on an FPGA board. It describes designing control logic to generate addresses and write enables to access a RAM such that the first data written is the first retrieved. The VHDL model will implement logic for a FIFO/stack with inputs like push, pop, and init and outputs like full, empty, nopush, and nopop flags. It lists the functions to be implemented as push, pop and read and describes the inputs, outputs, and group members for the project.

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84 views4 pages

EEP308 Computer Architecture Project Proposal: FIFO (First in First Out Queue) Control Logic

The document proposes a project to simulate a FIFO queue using assembly language and implement it on an FPGA board. It describes designing control logic to generate addresses and write enables to access a RAM such that the first data written is the first retrieved. The VHDL model will implement logic for a FIFO/stack with inputs like push, pop, and init and outputs like full, empty, nopush, and nopop flags. It lists the functions to be implemented as push, pop and read and describes the inputs, outputs, and group members for the project.

Uploaded by

srnankit
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EEP308 Computer Architecture

Project Proposal
FIFO(First In First Out Queue) Control Logic

Objective:

To simulate a FIFO( First In First Out) queue using assembly
language and implement on an FPGA board.

Description:

A common problem in design is constructing a FIFO from a RAM
by designing the control logic to generate the address (ADD)
and write enable (WE) to the RAM so that the first data word
written into the RAM is also the first data word retrieved from
the RAM. The VHDL model will implement the logic required to
implement the FIFO. In this case, the RAM is assumed to have
separate data inputs and outputs, an 8-bit address bus (ADD)
and an active high write enable (WE). The inputs to the
FIFO/Stack logic include PUSH, POP, INIT (all active high) in
addition to the rising edge triggered CLK input. The FIFO logic
will not only supply the address and write enable to the RAM,
but will also supply active high flags for FULL, EMPTY, NOPOP
and NOPUSH conditions.
The following functions are implemented:

Push: When an input (an n-bit binary number) is given at
the data_in input terminal at the active clock edge,
the binary number is stored on the stack and the
stack pointer is incremented by one.
Pop: The very first item stored on the stack is given as the
output and simultaneously removed from the
stack. The stack pointer is decremented by one.
Read: The last value stored on the stack is given as the
output at the active clock edge.

INPUTS

1. DATA_IN: Inputs n-bit binary number
2. CLK: Clock signal
3. INIT: Read operation takes place if 1
4. POP: When this signal is 1, pop operation takes
5. PUSH: When this signal is 1, push operation takes place.
OUTPUTS

1. DATA_OUT: Output n-bit binary number
2. FULL: This signal is 1 when the stack is full
3. EMPTY: This signal is 1 when the stack is empty
4. NOPUSH: exception is raised when the stack is full and push
function is asserted.
5. NOPOP: exception is raised when then stack is empty and pop
function is asserted.










BLOCK DIAGRAM





GROUP MEMBERS
Ankit Singh 2012EE20503
Aman Jakhar 2012EE20502
Sudarshan 2012EE20527

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