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    Lot To Lot Wafer To Wafer Die To Die: Process Variations

    Uploaded by

    Munish Jain
    Process variations can occur between production lots, wafers, and dies, as well as within individual devices, due to variations in parameters like impurity concentration, oxide thickness, and device dimensions. This causes electrical parameters like threshold voltage and sheet resistance to vary randomly. To account for these variations, designs typically use worst-case models, though this leads to overdesign. Instead, statistical design techniques aim to center the design such that most fabricated circuits meet specifications with minimal area overhead. Tools like Monte Carlo analysis help evaluate performance distributions under varied device parameters.

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    © All Rights Reserved
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    Lot To Lot Wafer To Wafer Die To Die: Process Variations

    Uploaded by

    Munish Jain
    81 views8 pages
    Process variations can occur between production lots, wafers, and dies, as well as within individual devices, due to variations in parameters like impurity concentration, oxide thickness, and device dimensions. This causes electrical parameters like threshold voltage and sheet resistance to vary randomly. To account for these variations, designs typically use worst-case models, though this leads to overdesign. Instead, statistical design techniques aim to center the design such that most fabricated circuits meet specifications with minimal area overhead. Tools like Monte Carlo analysis help evaluate performance distributions under varied device parameters.

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    Lect10 Process Var

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    Process variations can occur between production lots, wafers, and dies, as well as within individual devices, due to variations in parameters like impurity concentration, oxide thickness, and device dimensions. This causes electrical parameters like threshold voltage and sheet resistance to vary randomly. To account for these variations, designs typically use worst-case models, though this leads to overdesign. Instead, statistical design techniques aim to center the design such that most fabricated circuits meet specifications with minimal area overhead. Tools like Monte Carlo analysis help evaluate performance distributions under varied device parameters.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    81 views8 pages

    Lot To Lot Wafer To Wafer Die To Die: Process Variations

    Uploaded by

    Munish Jain
    Process variations can occur between production lots, wafers, and dies, as well as within individual devices, due to variations in parameters like impurity concentration, oxide thickness, and device dimensions. This causes electrical parameters like threshold voltage and sheet resistance to vary randomly. To account for these variations, designs typically use worst-case models, though this leads to overdesign. Instead, statistical design techniques aim to center the design such that most fabricated circuits meet specifications with minimal area overhead. Tools like Monte Carlo analysis help evaluate performance distributions under varied device parameters.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 8

    1

    Advanced VLSI Design CMPE 640


    Process Variations
    Process Variations
    The parameters of individual transistors vary from:
    Lot to lot (interprocess variation)
    Wafer to wafer (interprocess variation)
    Die to die (intraprocess variation)
    The observed random distribution of identically drawn devices is caused by:
    Variations in process parameters, e.g.,
    Impurity concentration densities
    Oxide thicknesses
    Diffusion Depths
    These result from non-uniform conditions during the deposition and/or the diffusion of the
    impurities (dopants).
    Changes in these parameters cause electrical parameters to vary, such as sheet resistance
    and threshold voltage.
    2
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    Causes for observed random distribution (cont):
    Variations in the dimensions of the devices:
    Limited resolution of the photolithographic process which causes W/L variations in
    MOS transistors.
    Many design parameters are totally uncorrelated.
    Variations in MOS transistor length are unrelated to variations in V
    T
    .
    Observations:
    Process variations impact the parameters that determine circuit performance, e.g., tran-
    sistor current.
    V
    T
    can vary due to (1) changes in oxide thickness, (2) substract, polysilicon and implant
    impurity levels and (3) surface charge.
    Accurate control of V
    T
    is very important.
    In the past, it varied up to 50% while today is is controlled within 25-50 mV.
    3
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    The main cause of variations in process transconductance, k'
    n
    is changes in oxide thick-
    ness.
    Variations in W and L are caused by the lithographic process.
    These variations are not correlated because W is determined in the field oxide step
    while L is defined in the poly and src/drain diffusion steps.
    These variations results in dramatic changes in device performance characteristics, in posi-
    tive and negative directions.
    This effects the design process, since your design is constrained by a specification, e.g., has
    to run at 3 GHz.
    In order to account for these variations, you may design your circuit using worst case val-
    ues for all device parameters.
    4
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    While safe, this approach is prohibitively conservative and results in severely overdesigned
    and hence uneconomical circuits.
    Manufacturer usually helps by providing fast and slow as well as nominal device models.
    An Example: Consider the performance impact of variations on an NMOS transistor in a
    0.25 m CMOS process.
    Assume that the device is in saturation with V
    GS
    = V
    DS
    = 2.5 V.
    This produces a drain current of 220 mA.
    The fast and slow models produce the following values:
    fast: I
    D
    = 265 mA (+20%)
    slow: I
    D
    = 182 mA (-17%)
    Here, W and L are modified by +/- 10%, V
    T
    by +/- 60mV and oxide thickness by (+/- 5%).
    5
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    Process variations are not the only source of variation that impacts performance.
    Variations in the power supply voltage can occur as well. A 10% variations can be
    expected.
    fast: V
    DD
    = 2.75 V: I
    D
    = 302 mA (+37%)
    slow: V
    DD
    = 2.2.5 V: I
    D
    = 155 mA (-30%)
    This illustrates that the current levels, and therefore the performance, can vary by as much
    as 100% over the extremes.
    In order to guarantee that the fabricated circuits meet performance requirements, under all
    circumstances, we need to make the transistor 42% (220 mA/155 mA) wider.
    This results in a severe area penalty.
    6
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    Fortunately, it is rare for all parameters to assume their worst (or best-case) values.
    Most designs will display a performance centered around the nominal design.
    Design for Manufacturability
    Objective is to center the design so that the majority of the fabricated circuit (99%) fall
    within the performance specifications, while keeping the area overhead minimal.
    Tools are available to help with this.
    Monte Carlo analysis involves simulating a circuit over a wide range of randomly
    chosen device parameters.
    The result is a distribution plot of design constraints (delay or noise sensitivity) that
    help determine if the nominal design is economically viable.
    7
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    For example, the impact of effective transistor channel length on the speed of an adder cell.
    Therefore SPICE simulations should be taken with a grain of salt.
    The device parameters used in the model are often lot-averaged results.
    In other words, these parameters are mean values and individual device parameters
    will vary statistically around these values.
    D
    e
    l
    a
    y

    (
    n
    s
    )
    1.1 1.5 1.3 1.7
    1.5
    1.7
    1.9
    L
    eff
    (nm)
    8
    Advanced VLSI Design CMPE 640
    Process Variations
    Process Variations
    Modeling inaccuracies and power supply variations are two sources of variation between
    actual and simulated device performances.
    Yet a third source of performance variation is temperature.
    Don't waste your time tweaking picoseconds out of your design using SPICE.

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