A

Compal confidential

Schematics Document
Mobile AMD S1G2 CPU with ATI
RX781(NB) & SB700(SB) core logic
3

2007-11-21
REV:0.1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

of

Rev
0.1
52

Compal Confidential

OPP Rachman AMD 14" Discrete - LA-4112P

Accelerometer
LIS3LV02DL-TR

Thermal Sensor
ADM1032ARMZ

VRAM
256 MB

AMD S1G2 CPU

Page 6

Page 37

Fan conn

BANK 0, 1, 2, 3

Dual Channel

638-PIN uFCPGA 638

72QFN

DDR2-SO-DIMM X2

DDR2 800MHz 1.8V

Clock Generator
SLG8SP626VTR

Page 8, 9

PC2-5300 (DDR2/667)
PC2-6400 (DDR2/800)

Page 22

Page 4
Page 4, 5, 6, 7

page 19, 20

Hyper Transport Link

DDR2 400MHz

Discrete
ATI M82-S

16X16

PCI-E Lane*16

Page 15,16,17,18,21

LVDS Panel
Interface Page

ATI RS780, RX781

RS780MN/CE
24
Page 10, 11, 12, 13, 14

USB2.0 X12

USB conn x3

CRT

Page 38

Page 23
1600x1200 max resolution at 75Hz

A-Link Express II
4X PCI-E

BT Conn

HDMI

Page 38

daughter board

Page 24

daughter board

Page 25

PCI-E BUS*5

Azalia (HDA I/F)

CardReader-JM385
5 in 1

Realtek
8102EL(10/100M)

Page 34

Page 32

Mini-Card* 1
WLAN Card

Chicony CNF7047

SATA Master-2
SATA Slave

Express Card

SATA Slave

Page 34

802.11a/b/g/n

USB WebCam

SATA Master-1

ATI SB700
Page 26,27,28,29,30

Page 34

MDC V1.5
3

CardReader CONN

LPC BUS

RJ45/11 CONN

daughter board

Page 41

Audio CKT

Page 32

TPA6017A2

Page 35
5 in 1:SD/MMC/MS/MSPro/XS
Support for RS-MMC, Memory Stick Duo and Memory Stick
Duo Pro, Micro-M2, Mini-SD, and MicroSD

KBC
ENE KB926

AMP & Audio Jack

Codec_IDT9271B7

Page 34

Page 36

SATA HDD Connector

Page 31

Page 40

SATA ODD Connector

LED

Page 31

Touch Pad CONN.

Page 41

Int.KBD

Page 41

Page 40

SATA 2nd HDD Option Connector

Page 31
15"&17" Only
e-SATA Connector

RTC CKT.
Page 26

SPI SPI ROM

25LF080A

Consumer IR
Page 36/42

Page 39

Page 38

Vista 32&64 bit supporttive

Energy star 4.0/EPEAT request compliant

Power On/Off CKT.

P41

Compal Secret Data

Security Classification

DC/DC Interface CKT.

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 43
A

2007/10/11

Issued Date

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

of

52

O MEANS ON

Voltage Rails

X MEANS OFF

Symbol Note :

: means Digital Ground

+5VS
+3VS

: means Analog Ground

+2.5VS

power
plane

+1.8VS

@ : means just reserve , no build

DEBUG@ : means just reserve for debug.

+1.5VS
+5VALW

+1.8V

+B
+3VL
+5VL
State

+1.1VS
+VGA_CORE

+0.9V

+3VALW

+1.2V_HT
+CPU_CORE_0

+1.2VALW

+CPU_CORE_1
+CPU_CORE_NB

S0

S1

S3

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

S5 S4/AC

SMBUS Control Table

SMB_EC_CK2

DDR SO-DIMM 0

A0

10100000

SMB_EC_DA2

DDR SO-DIMM 1

A4

10100100

SCL

CLOCK GENERATOR (EXT.)

D2

11010010

SDA

ACCELEROMETER

3A

00111010

DDC4CLK

Device

HEX

Address

EC SM Bus2 address
Device

HEX

Address

DDC3DATA
SCL0

16H

0001 011X b

ADI1032-2 CPU

9AH

1001 101X b

SDA0

24C16

A0H

1010 000X b

ADI1032-1 VGA

98H

1001 100X b

SCL1

98H

1001 100X b

SDA1
SCL2

VGA
M82-SE

DDC3CLK

Smart Battery
CPU SIC interface

KB926
VGA
M82-SE

DDC4DATA

EC SM Bus1 address

KB926

SDA2
SCL3
SDA3

VGA
M82-SE
SB700
SB700
SB700
SB700

X
V
X
X
X
X
X
X
X

V
X
X
X
X
X
X
X
X

X
V
X
X
X
X
X
X
X

X
X
X
X
X
V
X
X
X

X
X
X
X
X
V
X
X
X

2007/10/11

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

MINI CARD
Slot 1

X
X
X
X
X
X
V
X
X

Compal Secret Data

Security Classification
Issued Date

V
X
X
X
X
X
X
X
X

CLK CHIP

LCD

HDMI

CRT

G-Sensor

X
X
V
X
X
X
X
X
X

X
X
X
V
X
X
X
X
X

X
X
X
X

X
X
X
X
X
V
X
X
X

V
X
X
X
X

om

SMB_EC_DA1

ADDRESS

WL
SODIMM
I / II

l.c

HEX

THERMAL
SENSOR
CPU &
ADM1032

ai

DEVICE

SMB_EC_CK1

SERIAL
EEPROM

Title

Compal Electronics, Inc.

nf
@
ho
tm

I2C / SMBUS ADDRESSING

THERMAL
SENSOR
VGA M82-SE BATT
ADM1032

Notes List
Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

SOURCE

Sheet

he
x

of

Rev
0.1
52

VLDT CAP.

+1.2V_HT

250 mil
1
<10> H_CADIP[0..15]
<10> H_CADIN[0..15]

H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15] <10>

C1
4.7U_0805_10V4Z

H_CADON[0..15] <10>

C2
4.7U_0805_10V4Z

C3
0.22U_0603_16V4Z

C4
0.22U_0603_16V4Z

C5
180P_0402_50V8J

C6
180P_0402_50V8J

Near CPU Socket

+1.2V_HT
JCPUA

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

<10>
<10>
<10>
<10>

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AE2 +VLDT_B 1
C7
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

2
4.7U_0805_10V4Z
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

+5VS
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

9/20 SP02000D000/SP02000D700

PWM Fan Control circuit

<10>
<10>
<10>
<10>

JP2

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
<10>
<10>
<10>
<10>

HT LINK

D1
D2
D3
D4

1
D1
CH751H-40PT_SOD323-2

<10>
<10>
<10>
<10>

C8
4.7U_0805_10V4Z

C9
0.1U_0402_16V4Z

1.5A(+-60mV_dc,
+-75mV_ac)

GND
GND

1
2
5
6

Athlon 64 S1
Processor Socket

1
2

3
4

ACES_88231-02001
CONN@

+VCC_FAN
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@

1
2

D Q1

@ D2

G
FAN_PWM

RLZ5.1B_LL34

SI3456BDV-T1-E3_TSOP6

<40>

9/20 SP07000DM00/SP07000EQ00

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

of

52

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_A_CLK#0

C10
1.5P_0402_50V9C

DDR_A_CLK1
1

DDR_A_CLK#1

C11
1.5P_0402_50V9C
+1.8V
2

DDR_B_CLK0
1

R1
C14
1.5P_0402_50V9C

1K_0402_1%
1

DDR_B_CLK#0

R2
C15
1.5P_0402_50V9C

C12

1K_0402_1%
1

DDR_B_CLK#1

+MCH_REF

DDR_B_CLK1

C13

2
2
1000P_0402_25V8J
0.1U_0402_16V4Z

+0.9V

+0.9V
JCPUB
D10
C10
B10
AD10

Place them close to CPU within 1"

MEMZP/N=W/S=5mil/10mil
+1.8V

R4
1
1
R3

39.2_0402_1%
2
2
39.2_0402_1%

<8> DDR_CS0_DIMMA#
<8> DDR_CS1_DIMMA#

<8> DDR_CKE0_DIMMA
<8> DDR_CKE1_DIMMA

<8> DDR_A_CLK0
<8> DDR_A_CLK#0
<8> DDR_A_CLK1
<8> DDR_A_CLK#1

<8> DDR_A_MA[15..0]

<8> DDR_A_BS#0
<8> DDR_A_BS#1
<8> DDR_A_BS#2
<8> DDR_A_RAS#
<8> DDR_A_CAS#
<8> DDR_A_WE#

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

MEMZP
MEMZN

H16

RSVD_M1

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

J22
J20

MA_CKE0
MA_CKE1

T2
<8> DDR_A_ODT0
<8> DDR_A_ODT1

MEMZP AF10
MEMZN AE10

VTT1
VTT2
VTT3
VTT4

PAD

DDR_A_ODT0
DDR_A_ODT1

W10
AC10
AB10
AA10
A10

VTT_SENSE

Y10

MEMVREF

W17

750mA(+-50mV_dc,
+-75mV_ac)

VTT_SENSE

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

DDR_B_ODT0
DDR_B_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

MB_CKE0
MB_CKE1

J25
H26

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

N19
N20
E16
F16
Y16
AA16
P19
P20

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

PAD

T1 VTT_SENSE=W/S=10mil/10mil

PAD

T3

+MCH_REF

DDR_B_ODT0 <9>
DDR_B_ODT1 <9>
DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9>
DDR_CKE0_DIMMB <9>
DDR_CKE1_DIMMB <9>

DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
<9> DDR_B_DM[7..0]
DDR_B_MA[15..0] <9>

DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor
Socket

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

DDR_A_D[63..0] <8>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_DM[7..0] <8>

DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>

FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket

CONN@

om

JCPUC

<9> DDR_B_D[63..0]
DDR_A_CLK0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

CONN@

of

Rev
0.1
52

250mA(+-100mV_dc,
+-150mV_ac)

CPU_THERMTRIP#_R/ENTRIP2/H_THERMTRIP#=4mil/12mil

+2.5VDDA
VDDA=300mA
L1
3300P_0402_50V7K
1
2
FBM_L11_201209_300L_0805
1
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2

+2.5VS

A:Need to re-Link "SGN00000200"

+1.8V

R10
1
R5

2
10K_0402_5%
2
300_0402_5%
B

C16
100U_D2_10VM

CPU_THERMTRIP#_R

@ R6
1

0_0402_5%
2

1
R7

2
0_0402_5%

Q3
1

ENTRIP2

<44,46>

H_THERMTRIP# <27,40>

MMBT3904_NL_SOT23-3
JCPUD
1

F8
F9

C20

<22> CLK_CPU_BCLK

LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#

B7
A7
F10
C6

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

CPU_SIC
CPU_SID

AF4
AF5
AE6

SIC
SID
ALERT_L

R6
P6

HT_REF0
HT_REF1

2 3900P_0402_50V7K

R8
169_0402_1%

0718 Silego -- 216 ohm

<22> CLK_CPU_BCLK#

C21

2
3900P_0402_50V7K

Address:100_1100

+1.2V_HT

R13
R14

1
1

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

2
1

R15
300_0402_5%

<26>

LDT_RST#
1

C22
0.01U_0402_25V4Z
@

CLKIN_H
CLKIN_L

CPU_TEST23_TSTUPD
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

T9 PAD
T11 PAD

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN
1

R25

2 0_0402_5%

C939 0.1U_0402_16V4Z
R175

AD7

TEST23

H10
G9

TEST18
TEST19

E9
E8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

2
0_0402_5%

H_PROCHOT# <26>

+1.8V

R17
2

+1.8V
CPU_SVC
CPU_SVD

+1.8V sense no support

R22
1
1
R23

1K_0402_5%
2
2
1K_0402_5%

0718 AMD --> 1K ohm

PAD
PAD

DBREQ_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

T42
T43

+CPU_CORE_NB

VDD_NB_FB_H/L(Differential
pair)=10/5/5/5/10

R484 10_0402_5%
VDD_NB_FB_H 1
2
VDD_NB_FB_L 1
2
R485 10_0402_5%

Close to CPU

J7
H8

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

VDDIO_FB_H/L=10mil/10mil

VDD_NB_FB_H <50>
VDD_NB_FB_L <50>

TEST28_H
TEST28_L

TEST25_H
TEST25_L

AB8
AF7
AE7
AE8
AC8
AF8

R814
1

PAD
PAD
PAD
PAD
PAD
PAD

T5
T6

route as differential CPU_TEST28_H_PLLCHRZ_P

as short as possible /CPU_TEST28_L_PLLCHRZ_N (85ohm
testpoint under package Differential pair)

T7
T8
T10
T12

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

PAD
PAD

T13
T14

CPU_TEST29_H_FBCLKOUT_P
/CPU_TEST29_L_FBCLKOUT_N (85ohm
Differential pair)

H18
H19
AA7
D5
C5

FOX_PZ6382A-284S-41F_GRIFFIN
CONN@

34.8K_0402_1%~N

2.09V for Gate

C23
0.01U_0402_25V4Z
@

CPU_SIC

SMB_EC_DA2

SMB_EC_DA2 <21,40>

+1.8V

FDV301N_NL_SOT23-3
Q129 3

1 SMB_EC_CK2

SMB_EC_CK2 <21,40>

R36
300_0402_5%

Q127
FDV301N_NL_SOT23-3
2

+1.8VS

CPU_SID
R18
2
1
390_0402_5%
R19
2
1
390_0402_5%

+1.8V

LDT_STOP#=4mil/12mil

THERMDC_CPU
THERMDA_CPU

VDD_NB_FB_H
VDD_NB_FB_L

PAD

1
R11

W7
W8

H6
G6

20K_0402_5%
1

THERMDC
THERMDA

VDDNB_FB_H
VDDNB_FB_L

T4

CPU_PROCHOT#_1 .8

@ 300_0402_5%

VDD1_FB_H
VDD1_FB_L

+1.8VS

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V

CPU_VDD1_FB_H Y6
CPU_VDD1_FB_L AB6

H_PWRGD_CPU=4mil/12mil

+3VS

AF6
AC7
AA8

CPU_VDD1_FB_H/L(Differential<50> CPU_VDD1_FB_H
pair)=10/5/5/5/10
<50> CPU_VDD1_FB_L

Close to CPU

H_PWRGD_CPU

THERMTRIP_L
PROCHOT_L
MEMHOT_L

VDDIO_FB_H
VDDIO_FB_L

DBRDY
TMS
TCK
TRST_L
TDI

2
300_0402_5%

CPU_PROCHOT#_1.8/H_PROCHOT#=4mil/12mil

W9
Y9

R488 10_0402_5%

<26> H_PWRGD_CPU

CPU_SVC <50>
CPU_SVD <50>

VDDIO_FB_H
VDDIO_FB_L

G10
AA9
AC9
AD9
AF9

1
R9

+1.8V
CPU_SVC
CPU_SVD

VDD0_FB_H
VDD0_FB_L

+CPU_CORE_1
R489 10_0402_5%
1
2CPU_VDD1_FB_H
1
2CPU_VDD1_FB_L

R21
300_0402_5%

SVC
SVD

M11
W18
A6
A4

F6
E6

+CPU_CORE_0
R487 10_0402_5%
1
2CPU_VDD0_FB_H
1
2CPU_VDD0_FB_L
R486 10_0402_5%

LDT_RST#

KEY1
KEY2

CPU_VDD0_FB_H
CPU_VDD0_FB_L

+1.8VS

A9
A8

CPU_VDD0_FB_H/L(Differential<50> CPU_VDD0_FB_H
pair)=10/5/5/5/10
<50> CPU_VDD0_FB_L

CPU_ DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

LDT_RST#=4mil/12mil

VDDA1
VDDA2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

Place close to CPU wihtin 1.5"

+1.8V

0718 AMD , need check with AMD

CPU_LDT_REQ#=4mil/12mil

+1.8VS

R30
300_0402_5%
CPU_LDT_REQ#

C27
1
CPU_LDT_REQ# <11,26>

C24
0.01U_0402_25V4Z
@

+1.8V

1
C26
2
U2
1
THERMDA_CPU 2

THERMDC_CPU 3
2
2200P_0402_50V7K
4

2200p change to
1000p for ADT7421

SCLK

SMB_EC_CK2

D+

SDATA

SMB_EC_DA2

D-

ALERT#

GND

VDD

THERM#

ADM1032ARMZ-2REEL_MSOP8

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED

FOR REV. Ax SILICON ONLY.

HDT Connector
JP3
1
3
5
7
9
11
13
15
17
19
21
23

2
4
6
8
10
12
14
16
18
20
22
24
26

CPU_TEST27_SINGLECHAIN

R24

2 @ 300_0402_5%

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

R26
R27
R28
R29
R31
R32
R33
R34
R35

1
2
2
2
2
2
2
2
2

2
1
1
1
1
1
1
1
1

@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%

+3VS
5

+3VS

FDV301N, the Vgs is:

min = 0.65V
Typ = 0.85V
Max = 1.5V

U1
HDT_RST#

C25
0.01U_0402_25V4Z
@

LDT_STOP#

Y
3

2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
@ 220_0402_5% R40
2
1
@ 220_0402_5% R41

<11,26> LDT_STOP#

0.1U_0402_16V4Z

EC is PU to 5VALW

@ SAMTEC_ASP-68200-07

LDT_RST#
4

SB_PWRGD <27,40,50>

@ NC7SZ08P5X_NL_SC70-5

9/20 SP020016900
Address:100_1101

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

of

52

18A/7200mil/36vias

VDD(+CPU_CORE) decoupling.
+CPU_CORE_0

+CPU_CORE_0

+CPU_CORE_1

C30
330U_X_2VM_R6M

C28
330U_X_2VM_R6M

1
C31
330U_X_2VM_R6M

C29
330U_X_2VM_R6M

VDD_dc & VDDNB_dc

transient < 5us

Near CPU Socket

+CPU_CORE_0

+CPU_CORE_1

0.8V~1.1V, 3A(+-25mV_dc,
+-125mV_ac)
+CPU_CORE_NB

C32
22U_0805_6.3V6M

C33
22U_0805_6.3V6M

C34
22U_0805_6.3V6M

C35
22U_0805_6.3V6M

C36
22U_0805_6.3V6M

+CPU_CORE_0

C38
22U_0805_6.3V6M

C39
22U_0805_6.3V6M

2A(+-100mV_dc,
+-150mV_ac)

+1.8V

+CPU_CORE_1

C40
0.22U_0603_16V4Z

C37
22U_0805_6.3V6M

C41
0.01U_0402_25V4Z

C42
180P_0402_50V8J

C43
0.22U_0603_16V4Z

C44
0.01U_0402_25V4Z

C45
180P_0402_50V8J

Under CPU Socket

2

0.7V~1.2V, 18A/35W,
10A/20W(+-25mV_dc,
+-125mV_ac)

18A/7200mil/36vias
+CPU_CORE_1

JCPUE
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket

CONN@

+CPU_CORE_NB
VDDIO decoupling.

+CPU_CORE_NB

+1.8V

C52
22U_0805_6.3V6M

2
1

C46
22U_0805_6.3V6M

C47
22U_0805_6.3V6M

C48

C49

C50

C53
22U_0805_6.3V6M

C54
22U_0805_6.3V6M

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket

C51

CONN@
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2
2
2
2

+0.9V

Under CPU Socket

decoupling.

JCPUF
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

Near Power Supply

VTT decoupling.

C: Change to NBO CAP

+ C59
220U_Y_4VM
2

Between CPU Socket and DIMM

+1.8V
+0.9V
1

C55
0.22U_0603_16V4Z

C56
0.22U_0603_16V4Z

C57
0.22U_0603_16V4Z

+1.8V

C61
0.01U_0402_25V4Z

C58
0.22U_0603_16V4Z
1

+1.8V

C60
0.01U_0402_25V4Z

180PF Qt'y follow the distance between

CPU socket and DIMM0. <2.5inch>
1

C62
180P_0402_50V8J

C63
180P_0402_50V8J

C64
180P_0402_50V8J

C67
4.7U_0805_10V4Z

C68
0.22U_0603_16V4Z

C69
0.22U_0603_16V4Z

C70
1000P_0402_25V8J

C71
1000P_0402_25V8J

C72
180P_0402_50V8J

C73
180P_0402_50V8J

Near CPU Socket Right side.

C65
180P_0402_50V8J

+0.9V

A: Add C165 and C176

to follow AMD Layout
review recommand for
EMI

+1.8V

C66
4.7U_0805_10V4Z

C79
4.7U_0805_10V4Z

C80
4.7U_0805_10V4Z

C81
0.22U_0603_16V4Z

C82
0.22U_0603_16V4Z

C83
1000P_0402_25V8J

C84
1000P_0402_25V8J

C85
180P_0402_50V8J

C86
180P_0402_50V8J

C77
4.7U_0805_10V4Z

+ C78
220U_Y_4VM
@

Near CPU Socket Left side.

om

C76
4.7U_0805_10V4Z

Compal Secret Data

Security Classification
2007/10/11

Issued Date

ai

C75
4.7U_0805_10V4Z

C: Change to NBO CAP

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

nf
@
ho
tm

AMD CPU S1G2 PWR & GND

Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

C74
4.7U_0805_10V4Z

Sheet

he
x

l.c

1
1

of

Rev
0.1
52

+V_DDR_MCH_REF
+1.8V

DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_DM[0..7]

DDR_A_DM[0..7] <5>

DDR_A_DM0
DDR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7

DDR_A_DQS#[0..7]

8
7
6
5

DDR_A_DQS[0..7] <5>

DDR_A_MA[0..15]

DDR_A_D12
DDR_A_D13

DDR_A_MA11
DDR_A_MA14
DDR_A_MA7
DDR_A_MA6

DDR_A_D[0..63] <5>

DDR_A_MA[0..15] <5>

DDR_A_MA15
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_BS#2

DDR_A_DQS#[0..7] <5>

DDR_A_DM1
DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>
DDR_A_D14
DDR_A_D15

+1.8V

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2

DDR_A_D26
DDR_A_D27
<5> DDR_CKE0_DIMMA
<5> DDR_A_BS#2

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<5> DDR_A_BS#0
<5> DDR_A_WE#
<5> DDR_A_CAS#
<5> DDR_CS1_DIMMA#
<5> DDR_A_ODT1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

<9,22,27,37> SMB_CK_DAT0
<9,22,27,37> SMB_CK_CLK0
+3VS

1
C103
0.1U_0402_16V4Z

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

R43
1K_0402_1%

DDR_A_D20
DDR_A_D21
+V_DDR_MCH_REF

+V_DDR_MCH_REF <9>

DDR_A_DM2
DDR_A_D22
DDR_A_D23

C95

C96

2
1000P_0402_25V8J

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

R44
1K_0402_1%

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <5>

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

C87
C88

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1

C90
C89

C91
C92

C93
C94

1
1

1
1

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4

DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_CAS#
DDR_A_WE#

47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4

1
C100
1
C99

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
RP7
DDR_A_RAS#
8
1
DDR_A_ODT0
7
2
DDR_A_MA13
6
3
DDR_CS0_DIMMA#
5
4

1
C102
1
C101

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_D30
DDR_A_D31

47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4

47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

1
2
3
4

47_0804_8P4R_5%
RP3
8
1
7
2
6
3
5
4

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1

DDR_A_D16
DDR_A_D17

+1.8V

+0.9V
RP1
DDR_A_D[0..63]

DDR_A_D4
DDR_A_D5

DDR_A_D10
DDR_A_D11

+1.8V

JP4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C98
C97

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
3

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

TYCO_292527-4
CONN@

9/20 SP07000ET00/SP07000GN00

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DDRII SO-DIMM 0

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

of

52

+1.8V

+1.8V

DDR_B_D0
DDR_B_D1
C104

2
1000P_0402_25V8J

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

+1.8V

+0.9V

JP5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> +V_DDR_MCH_REF

RP8

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_B_D[0..63]
DDR_B_D4
DDR_B_D5

DDR_B_DM[0..7]

DDR_B_DM0

DDR_B_DQS[0..7]

DDR_B_D6
DDR_B_D7

DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

DDR_B_D12
DDR_B_D9

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#

DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>

8
7
6
5

1
2
3
4

2
C105
1
C106

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C108
1
C107

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C109
1
C110

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C111
1
C112

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C114
1
C113

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C116
1
C115

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C118
1
C117

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%

DDR_B_MA[0..15] <5>

RP9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

DDR_B_DQS#[0..7] <5>

8
7
6
5

DDR_B_DM1

1
2
3
4

47_0804_8P4R_5%
DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>

RP10
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_CKE0_DIMMB
DDR_B_BS#2

DDR_B_D14
DDR_B_D15

8
7
6
5

1
2
3
4

47_0804_8P4R_5%

DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
2

<5> DDR_B_BS#2

DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

<5> DDR_B_BS#0
<5> DDR_B_WE#
<5> DDR_B_CAS#
<5> DDR_CS1_DIMMB#
<5> DDR_B_ODT1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
<8,22,27,37> SMB_CK_DAT0
<8,22,27,37> SMB_CK_CLK0
1

DDR_B_D20
DDR_B_D16

RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_DM2
DDR_B_D22
DDR_B_D23

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
RP12

DDR_B_D28
DDR_B_D29

DDR_B_MA10
DDR_B_BS#0
DDR_B_MA1
DDR_B_MA3

DDR_B_DQS#3
DDR_B_DQS3

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
DDR_B_D30
DDR_B_D31

RP13

DDR_CKE1_DIMMB

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_CKE1_DIMMB <5>

DDR_B_MA15
DDR_B_MA14

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

RP14
DDR_B_RAS#
DDR_B_BS#1
DDR_B_ODT0
DDR_B_MA13

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13

Cross between +1.8V and +0.9V power plan

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS

FOX_AS0A426-N8RN-7F
CONN@

9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DDRII SO-DIMM 1

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

C119
0.1U_0402_16V4Z

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

201
202

+3VS
4

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

om

<5> DDR_CKE0_DIMMB

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
VSS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D21
DDR_B_D17

of

Rev
0.1
52

PCIE_GTX_C_MRX_P[0..15]

<15> PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

<15> PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] <15>

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15] <15>

U3B

<34>
<34>
<33>
<33>
<32>
<32>

PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

PCIE I/F

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

RS780M_FCBGA528

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

UMA@

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

C121 1

C123 1

C125 1

C127 1

C129 1

C131 1

C133 1

C135 1

C137 1

C139 1

C141 1

C143 1

C145 1

C147 1

C149 1

C151 1

C120 1
0.1U_0402_16V7K

0.1U_0402_16V7K

C122 1
0.1U_0402_16V7K
C124 1
0.1U_0402_16V7K
C126 1
0.1U_0402_16V7K
C128 1
0.1U_0402_16V7K
C130 1
0.1U_0402_16V7K
C132 1
0.1U_0402_16V7K
C134 1
0.1U_0402_16V7K
C136 1
0.1U_0402_16V7K
C138 1
0.1U_0402_16V7K
C140 1
0.1U_0402_16V7K
C142 1
0.1U_0402_16V7K
C144 1
0.1U_0402_16V7K
C146 1
0.1U_0402_16V7K
C148 1
0.1U_0402_16V7K
C150 1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

Polarity inversion
1

Polarity inversion

Polarity inversion

New Card(delete)
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

C154 1
C155
1
C156 1
C157
1
C158 1
C159
1

0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2

PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3

CardReader

<34>
<34>
<33>
<33>
<32>
<32>

WLAN
LAN10/100
<4> H_CADOP[0..15]

TV Tuner(delete)

<4> H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

AC8 CALRP
AB8 CALRN

R55
R56

C162
C163
C164
C165
C166
C168
C169
C167

1
1
1
1
1
1
1
1

1
1

2
2

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

1.27K_0402_1%
2K_0402_1%

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>

H_CADIP[0..15]
H_CADIN[0..15]

H_CADIP[0..15] <4>
H_CADIN[0..15] <4>

U3A

+1.1VS

Place them close to NB within 1"

CALRP/N=W/S=5mil/10mil

RS780M Display Port Support (muxed on GFX)

GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1

SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH

SA00001ZG20(A12) S IC 216-0674008-00 A12 RS780M FCBGA 0FH

H_CADOP[0..15]
H_CADON[0..15]

<4>
<4>
<4>
<4>

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

<4>
<4>
<4>
<4>

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

301_0402_1%

1 R57

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

M22
M23
R21
R20

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2

RXCALRP
RXCALRN

Place them close to NB within 1"

RXCALRP/N=W/S=5mil/10mil

C23
A24

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

TXCALRP
TXCALRN

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GFX

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

RS780M_FCBGA528
UMA@

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

<4>
<4>
<4>
<4>

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

<4>
<4>
<4>
<4>

1 R58

2 301_0402_1%

Place them close to NB within 1"

TXCALRP/N=W/S=5mil/10mil

NEED CHECK R68 & R69 WITH AMD

4

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780-HT/PCIE

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

10

of

52

+3VS
2

+1.8VS

@ R87
4.7K_0402_5%
1

G
3

NB_LDTSTOP#

D
FDV301N_NL_SOT23-3

+AVDD1 For DAC analog power

+AVDD2 For DAC digital power
+AVDDQ For DAC Bandgap
+3VS

+3VS
+1.8VS
2

+1.8VS

@ R84
4.7K_0402_5%

@ Q5

AVDD=100mA

L2 +AVDD1 20mil
1
2 +AVDD1
0_0603_5%
1
L4+AVDD2 20mil
@ C170
1
2 +AVDD2
2.2U_0603_6.3V4Z
0_0603_5%
1
2

L6 +AVDDQ 20mil
1
2 +AVDDQ @ C172
0_0603_5%
2.2U_0603_6.3V4Z
2
1

<6,26> CPU_LDT_REQ#

+1.8VS

NB_ALLOW_LDTSTOP

FDV301N_NL_SOT23-3

@ C175
2.2U_0603_6.3V4Z
2
R1171

U3C

1
0_0402_5%

+1.1VS

L9
+NB_PLLVDD Fro Graphic PLL power
1
2
0_0603_5%
+NB_HTPVDD For Graphic PLL power
1
L7
@ C178
1
2
0_0603_5%
2.2U_0603_6.3V4Z
1
2
+1.8VS
L10
@ C176
+NB_PLLVDD=W/S=20/10mil
+NB_PLLVDD
1
2
+NB_HTPVDD +NB_HTPVDD=W/S=20/10mil
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
L11
C179
+1.8VS

+1.8VS

1
2
BLM18PG121SN1D_0603
C180
2.2U_0603_6.3V4Z

E17
F17
F15

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

G18
G17
E18
F18
E19
F19

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

A11
B11
F8
E8

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12
D14
B12

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

D8
A10
C10
C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

<22> CLK_NBHT
<22> CLK_NBHT#

C25
C24

HT_REFCLKP
HT_REFCLKN

<22> NB_OSC_14.318M

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

1
2
R71
158_0402_1%

+1.8VS

1
2
R72
90.9_0402_1%

RS780: 158-? 1% series termination resistor and 90.9-? 1% resistor

to GND to limit signal swing to 1.1 V. Also made provision for 0.5
* 1.1 V with a resistor divider at the REFCLK_N ball.

1
R371

R66 0_0402_5%
1
2 NB_RESET#
NB_PW RGD
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
2
10K_0402_5%

<22> NBGFX_CLK
<22> NBGFX_CLK#

<22> CLK_SBLINK_BCLK
<22> CLK_SBLINK_BCLK#

+3VS

<14>

2
1
R88 10K_0402_5%

AUX_CAL

GFX_REFCLKP
GFX_REFCLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
STRP_DATA

G11

RSVD

C8

Strap pin

A22
B22
A21
B21
B20
A20
A19
B19

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

+VDDLTP18 20mil

T2
T1

B10

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

H17
+VDDA18PCIEPLL=W/S=20/10mil VDDA18HTPLL

+VDDA18PCIEPLL

Install when SB700 A12 use

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

+VDDA18HTPLL

2.2U_0603_6.3V4Z
2

<14,15,26,32,33,34,39,40> PLT_RST#
<27> NB_PWRGD

+1.1VS

F12
E12
F14
G15
H15
H14

+VDDA18HTPLL=W/S=20/10mil
1

CRT/TVOUT

1
0_0402_5%

PLL PWR
LVTM

2
R1170

PM

@ Q6
1

CLOCKs

<6,26> LDT_STOP#

+VDDLTP18
+VDDLT18
2
1
@ C173
0.1U_0402_16V4Z

L3
0_0603_5%

+VDDLT18 20mil

@ C171
2.2U_0603_6.3V4Z

L5
0_0603_5%

+1.8VS

+VDDLTP18/+VDDLT18 For
LVDS/DVI/HDMI PLL power
+1.8VS

@ C174
4.7U_0805_10V4Z

0.08A

flash issue check IALAA

MIS.

TMDS_HPD(NC)
HPD(NC)

D9
D10

SUS_STAT#(PWM_GPIO5)

D12

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

D13

AUX_CAL(NC)

1
R77

2
0_0402_5%

SUS_STAT# <27>
SUS_STAT_R# <14>

Strap pin
NB temp to SB

1
2
R80
1.8K_0402_5%

RS780M_FCBGA528

UMA@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

11

of

Rev
0.1
52

U3D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

SBD_MEM/DVO_I/F

PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_COMPP(NC)
MEM_COMPN(NC)

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

+1.8VS
+1.1VS

+1.8VS=W/S=20/10mil For Memory PLL power

+1.1VS=W/S=20/10mil For Memory PLL power

RS780M_FCBGA528
UMA@

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 Side-Port DDR2 SDRAM

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

12

of

52

U3F

+VDDHT >120mil
(power plan)

+VDDHT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C2081
1 C206 1
1
1
C210

4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.25A/2vias

L22
2

+1.8VS

+VDDA18PCIE >20mil
(power plan)
+VDDA18PCIE

FBMA-L11-201209-221LMA30T_0805

C235
4.7U_0805_10V4Z

1
C246

1
C236

1
C237

1
C238

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

1
C239

4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.8VS

+1.8VS >20mil
0_0603_5%
2
1
R1054
3

F9
G9
AE11
AD11

+1.8VS
+1.8V_VDD_MEM

+1.8V_VDD_MEM

+1.8V_VDD_MEM >20mil
+1.8V_VDD_MEM For Memory I/O power or DVO I/O power

C251
1U_0402_6.3V4Z

1
2
2

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

L20 1
2
FBMA-L11-201209-221LMA30T_0805
L21 1
2
FBMA-L11-201209-221LMA30T_0805

+1.1VS

+NB_VDDC

VDD_CORE=5A

7A/16vias

330U_D2E_2.5VM_R15

C245

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C233

1
C229

+NB_VDDC >300mil
(power plan)

10U_0805_10V4Z

1
C228

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C232

1
C227

2
2
2
2
1
1

10U_0805_10V4Z

+1.35VS for A11

1
C226

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

1
1
1
1
2
2

C244

1
C225

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

C220
C219
C222
C221
C224
C223

0.1U_0402_16V4Z

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

10U_0805_10V4Z

C212

C231

+VDDHTTX

2
1
FBMA-L11-201209-221LMA30T_0805

+1.2V_HT

H18
G19
F20
E21
D22
B23
A23

10U_0805_10V4Z

C211

0.1U_0402_16V4Z

+VDDHTTX >45mil
(power plan)

0.5A/4vias

L19

0.1U_0402_16V4Z

+1.1VS

+VDDA11PCIE

C230

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

0.1U_0402_16V4Z

C216
2
2
2
0.1U_0402_16V4Z

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

C243

C215
4.7U_0805_10V4Z

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1 C217 1
1
C214
C218

FBMA-L11-201209-221LMA30T_0805

J17
K16
L16
M16
P16
R16
T16

C242

+VDDHTRX

L17
1
2
FBMA-L11-201209-221LMA30T_0805

0.7A/4vias
VDDA_12=2.5A

U3E

+VDDHTRX >70mil
(power plan)

0.45A/3vias

L18
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C241

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C207

C240

0.1U_0402_16V4Z

C247

C209
4.7U_0805_10V4Z

+VDDA11PCIE >300mil
(power plan)

0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

POWER

+1.1VS

0.1U_0402_16V4Z

0.6A/4vias
L16

C234

+
2

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

PART 6/6

GROUND

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

RS780M_FCBGA528
UMA@

AE10
AA11
Y11
AD10
AB10
AC10
H11
H12

0.15A/2vias

RS780M_FCBGA528
UMA@
C252
1U_0402_6.3V4Z
SIDE@

+3VS

+3VS >20mil
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z

VDD18_MEM For Memory transform power

2
2

C250
C253

Just for RS780M A11 version boot issue

+1.8VS

@ U64
1 VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

+3VS

1
@ C1064

@ R1015
1K_0402_1%
2

2 10U_0805_10V4Z

1
@ C1065
2

1U_0603_10V6K

G2992F1U_SO8
+VREF1.35V
1

+1.35VS

1
@ C1067

@ C1068
0.1U_0402_16V7K

10U_0805_10V4Z

om

2
@ C1066

l.c

3K_0402_5%

0.1U_0402_16V7K

Compal Secret Data

Security Classification
2007/10/11

Issued Date

ai

2
G

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

nf
@
ho
tm

2
0_0402_5%

RS780 PWR/GND
Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

1
@ R1017

VLDT_EN#

<43>

Sheet

he
x

@ R1016
1

@ Q163
2N7002_SOT23-3

13

of

Rev
0.1
52

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

2
@ R101
2
R102

<16,23> CRT_VSYNC

1
1K_0402_5%
1
1K_0402_5%

Enables the Test Debug Bus using GPIO.

1 : Disable (RS740) Enable (RX780, RS780)
0 : Enable (Rs740)
Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

+3VS

DFT_GPIO1: LOAD_EEPROM_STRAPS
1
@ R104

<11> AUX_CAL

RS780 DFT_GPIO1

D4
2

<11> SUS_STAT_R#

2
150_0402_1%
@ CH751H-40PT_SOD323-2
1

PLT_RST#

Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
<11,15,26,32,33,34,39,40>
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RX780: Enables the Test Debug Bus using PCIE bus

1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS780 use HSYNC to enable SIDE PORT (internal pull high)

2
R107 @

<16,21,23> CRT_HSYNC

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

1
3K_0402_5%

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 STRAPS

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

14

of

52

PCIE_GTX_C_MRX_P[0..15]

<10> PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

<10> PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

<10> PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

<10> PCIE_MTX_C_GRX_N[0..15]

U5A
PART 1 OF 6

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

AC30
AC31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AA28
AA27

PEG_M_RXP15
PEG_M_RXN15

C1077 1
C1078 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

AC29
AB29

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AA25
AA24

PEG_M_RXP14
PEG_M_RXN14

C1079 1
C1080 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

AB31
AB30

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

Y28
Y27

PEG_M_RXP13
PEG_M_RXN13

C1081 1
C1082 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

AA31
AA30

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

Y25
Y24

PEG_M_RXP12
PEG_M_RXN12

C1083 1
C1084 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

W30
W31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

V28
V27

PEG_M_RXP11
PEG_M_RXN11

C1085 1
C1086 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

W29
V29

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

V25
V24

PEG_M_RXP10
PEG_M_RXN10

C1087 1
C1088 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

V31
V30

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

T28
T27

PEG_M_RXP9
PEG_M_RXN9

C1089 1
C1090 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

U31
U30

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

T25
T24

PEG_M_RXP8
PEG_M_RXN8

C1091 1
C1092 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

P30
P31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

P28
P27

PEG_M_RXP7
PEG_M_RXN7

C1093 1
C1094 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

P29
N29

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

P25
P24

PEG_M_RXP6
PEG_M_RXN6

C1095 1
C1096 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

N31
N30

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

M28
M27

PEG_M_RXP5
PEG_M_RXN5

C1097 1
C1098 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

M31
M30

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

M25
M24

PEG_M_RXP4
PEG_M_RXN4

C1099 1
C1100 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

K30
K31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

L28
L27

PEG_M_RXP3
PEG_M_RXN3

C1101 1
C1102 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

K29
J29

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

L25
L24

PEG_M_RXP2
PEG_M_RXN2

C1103 1
C1104 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

J31
J30

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

J28
J27

PEG_M_RXP1
PEG_M_RXN1

C1105 1
C1106 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

H31
H30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

G28
G27

PEG_M_RXP0
PEG_M_RXN0

C1107 1
C1108 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0

PCIE LANE REVERSAL

P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E

PCIE LANE REVERSAL

Clock
<22> CLK_PCIE_VGA
<22> CLK_PCIE_VGA#

<11,14,26,32,33,34,39,40> PLT_RST#

AD29
AD30

PCIE_REFCLKP
PCIE_REFCLKN
SM BUS

AC28
AC27

NC_SMBCLK
NC_SMBDATA

AG25

PERSTB

Calibration
PCIE_CALRN

R1057 2K_0402_1%
2
AF25 PCIE_CALRN 1

PCIE_CALRP

AE25 PCIE_CALRP 1 R1058 2

1.27K_0402_1%

NC
NC

+1.1VS

PCIE_CALRN/P==W/S=5mil/10mil

AE23
AH30

216-0707001-00/M82-S_BGA632

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S PCIE interface

Size

Document Number

LA-4112P
Date:

Wednesday, November 21, 2007

1

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

15

of

Rev
0.1
52

polarity swap for ATI commond

+1.8VS

PART 2 OF 6

BLM18PG121SN1D_0603
2
1
L97

AL5
AK5

1U_0402_6.3V4Z

+VGA_CORE

+MPVDD
1

AL6
AK6

C1114
C1112

2
10U_0603_4V6M

C1113

AK8
AL8

2
0.1U_0402_16V4Z

<21>

PSYNC

BLM18PG121SN1D_0603
L100
0.1U_0402_16V4Z +DPLL_PVDD
2
1
1
1
1
+1.8VS
C1126
1U_0402_6.3V4Z
C1125
C1124
2
2
2
10U_0603_6.3V6M

+1.8VS

R1059

0.1U_0402_16V4Z +PCIE_PVDD
1
1
1
C1133
C1135
C1134 1U_0402_6.3V4Z

10U_0603_6.3V6M

BLM18PG121SN1D_0603
R1063
0.1U_0402_16V4Z +DPLL_VDDC
2
1
+1.1VS
1
1
1
C1136
C1137
C1138
1U_0402_6.3V4Z
2
2
2
10U_0603_6.3V6M

<21>
<21>
<21>
<21>
<21>
<21>

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

<40>

+1.8VS

1
10K_0402_5%

ENBKL

R1067
2

+3.3V_DELAY

<51> VGA_PWRSEL
<22> 27M_SSC

1
2
R1162
0_0402_5%

C1151
0.1U_0402_16V4Z

+3.3V_DELAY

2
10K_0402_5%

VGA_CLKREQ#
T47
T48
T49
T50

PAD
PAD
PAD
PAD

T51 PAD
T52 PAD
U4

REFOUT

XOUT MODOUT

VSS

5
1
@ R1163
3 XIN
VDD 4
1
@ C1273
ASM3P2872A

0.1U_0402_16V4Z

2 27M_SSC_R
33_0402_5%

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DPB_VDDR
DPB_VDDR

AK13
AL13

W1

DVPCLK

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

AL12
AK12
AJ11
AH9
AH11

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

AJ8
AF7
AG7
AJ7
AH7

+3VS
1
@ C1274
1U_0402_6.3V4Z

52mA
68mA

Y8
Y7
V8
AH6
AG6

+VGA_VREF AC11
AH12
AG12

DPLL_PVDD
DPLL_PVSS

+PCIE_PVDD

AH31

PCIE_PVDD

VGA input level is 1.8V

27MCLK

IN

GND

Y8
OUT

R1076
1K_0402_5%

3
2

27MHz_16PF_6P27000126

@
CV2
2 22P_0402_50V8J

BLUE

RSET

AJ28

AVDD

AL29

AVSSQ

AH28

VDD1DI

AJ27

VSS1DI

AJ26

R2
R2B

AL17
AK17

G2
G2B

AL15
AK15

B2
B2B

AL14
AK14

AJ17

MPVDD
MPVSS

AJ31

XTALIN

AJ30

XTALOUT

AH26

TESTEN

AD12

PLLTEST

<25>

RED

<23>

GREEN

<23>

BLUE

AG18
AH18

LPVDD
LPVSS

1
R1061
1
R1062
1
R1064

<23>

1
2
R1065 499_0402_1%

C1130

+VDD1DI

A2VDD

AH14

+A2VDD

A2VDDQ

AH16

+A2VDDQ

A2VSSQ

AG16

2
1
+1.8VS
L103
BLM18PG121SN1D_0603

C1132
2
0.1U_0402_16V4Z

2
1
+1.8VS
L104
BLM18PG121SN1D_0603
C1141
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
1

1
C1143

C1144
10U_0603_6.3V6M

1
+1.8VS
L105
BLM18PG121SN1D_0603

1U_0402_6.3V4Z
2

C1140

1
C1149

L107
2

0_0603_5%
1
+1.8VS

@ 10U_0603_6.3V6M
1
1
C1145

C1146

2
2
@ 0.1U_0402_16V4Z

C1150
2 @ 1U_0402_6.3V4Z

L106
2

0_0603_5%
1
+3.3V_DELAY

C1147
2 @ 1U_0402_6.3V4Z

@ 0.1U_0402_16V4Z
1
R1073

2
715_0402_1%
LCD_DDC_CLK <24>
LCD_DDC_DAT <24>

LCD

AF4
AH4

VGA_DDC_DAT <23>
VGA_DDC_CLK <23>

CRT

DDC4DATA_DP4_AUXN
DDC4CLK_DP4_AUXP

AF9
AG9

HDMIDAT_VGA <25>
HDMICLK_VGA <25>

HDMI

D+
D-

<21>
<21>

thermal

D+/D-=others 20mil/10mil/10mil/10mil/others 20mil

Compal Secret Data

Security Classification
Issued Date

2007/10/11

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C1131

C1139

Title

+LPVDD
1

2
2
0.1U_0402_16V4Z

1
C1148

DDC3DATA_DP3_AUXN
DDC3CLK_DP3_AUXP

AE5
AE4

LVDS_ACLK+ <24>
LVDS_ACLK- <24>
LVDS_A0+ <24>
LVDS_A0- <24>
LVDS_A1+ <24>
LVDS_A1- <24>
LVDS_A2+ <24>
LVDS_A2- <24>

100mA

AC5
AC4

DPLUS
DMINUS

48mA

2
2
@ 10U_0603_6.3V6M

AA5
AA4

AE14

AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22

AF18

TS_FDO

1
C1142

AE16
AF16

AE18

TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

100mA

1U_0402_6.3V4Z
2

V2SYNC
H2SYNC

AG14

LVDS_BCLK+ <24>
LVDS_BCLK- <24>
LVDS_B0+ <24>
LVDS_B0- <24>
LVDS_B1+ <24>
LVDS_B1- <24>
LVDS_B2+ <24>
LVDS_B2- <24>

100mA

+AVDD

AJ15

R2SET

TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23

10U_0603_6.3V6M
1

VSS2DI

VGA_ENVDD <24>

LVDS channel

216-0707001-00/M82-S_BGA632
2
1
+1.1VS
L102
BLM18PG121SN1D_0603

C1129

2
10U_0603_6.3V6M

RED

DDC2DATA
DDC2CLK

THERMAL

LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR

200mA

GREEN

DDC1DATA
DDC1CLK

TEST

AF23
AF21
AL18
AJ22
AJ25
AK18
AK23
AK25
AJ21
AL23
AL25

T46 PAD

AA7
AC6

CRT_HSYNC <14,21,23>
CRT_VSYNC <14,23>

AJ14

DPLL_VDDC

2
0.1U_0402_16V4Z

40mA

C1128
2

LVDDC
LVDDC

2
1U_0402_6.3V4Z

HPD

AJ29
AH29

PLL &
XTAL

C1117

2
10U_0603_6.3V6M

BLUE

COMP

SCL
SDA
SERIAL
BUSES

C1127

C1123

VARY_BL
Control
DIGON

150_0402_1%
2

VDD2DI

216-0707001-00/M82-S_BGA632
@
CV1
22P_0402_50V8J

G
GB

1
1

XTALOUT

A9
B9

R1075
100_0402_5%

XTALOUT

GND

+DPLL_VDDC AE12

27MCLK

80mA

27M_OUT

75_0402_1%
1
2
R1074

230mA

+MPVDD

RED

+LVDDC

AJ18
AH20

2
1
+1.1VS
L101
BLM18PG121SN1D_0603

1U_0402_6.3V4Z
1
1

LVDDR
LVDDR

80mA

200mA

C1122
2

GREEN

VREFG

+DPLL_PVDD

+DPB_VDDR

AL27
AK27

AK29
AK30

C1121

0.1U_0402_16V4Z

AL28
AK28

PART 6 OF 6

AF20
AG20

C1120

R1060
1

2
0.1U_0402_16V4Z

C1116

2
10U_0603_6.3V6M

U5F

320mA
C1111

2 10U_0603_6.3V6M

0.1U_0402_16V4Z

R
RB

AL26
AK26

C1119

+1.8VS

1U_0402_6.3V4Z
+DPA_VDDR 1
1

AA8

B
BB

DAC2 (TV/CRT2)

C1118
2
2
0.1U_0402_16V4Z

AG11

HSYNC
VSYNC

DAC1 / CRT

GEN_A
GEN_B
GEN_C
GEN_D_HPD4
GEN_E

27M_CLK

<22>

V2
V1
W3

GPIO_0
GPIO_1
GPIO_2
GENERAL
GPIO_3
PURPOSE
GPIO_4
I/O
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_JMODE
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

VGA_CTF

Spread spectrum

R1164
0_0402_5%

AJ12
AJ13

Y4
V3
V4
V5
U3
U2
T4
T5
T7
T8
R1
R2
R3
P1
P3
N1
N2
P4
P7
P8
P5
V7
N3
Y5
M4
M5
M7
M8
L8

27M_SSC_R

SI: Per EMI request add SSC chip

27M_OUT

DPA_VDDR
DPA_VDDR

C1115

L99
2
1
1 BLM18PG121SN1D_0603

+1.8VS_DPA 1U_0402_6.3V4Z
1
1

1U_0402_6.3V4Z
1

1
2
L98
1
BLM18PG121SN1D_0603

TMDS_B_DATA2# <25>
TMDS_B_DATA2 <25>

40mA

DVPCNTL_MVP_0
DVPCNTL_MVP_1

HPD1

TMDS_B_DATA1# <25>
TMDS_B_DATA1 <25>

AL11
AK11

AE11
AF11

DP_CALR

+1.8VS

+LVDDR
1

C1110

2
10U_0603_6.3V6M

TMDS_B_DATA0# <25>
TMDS_B_DATA0 <25>

AL10
AK10

DPB_PVDD
DPB_PVSS

C1109

TMDS_B_CLK# <25>
TMDS_B_CLK <25>

AJ9
AJ10

DPA_PVDD
DPA_PVSS

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11 EXT TMDS
DVPDATA_12 DVO
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

GPIO4
GPIO5
GPIO6

1
R1070 1K_0402_5%

TX2M_DPB3P
TX2P_DPB3N

Y1
Y2
Y3
AA2
AA3
AB1
AB2
AB3
AC1
AC3
AD1
AD2
AD3
AF3
AG3
AH3
AG1
AH2
AH1
AJ3
AJ1
AJ2
AK2
AK3

<21> THM_ALERT#

<21> SCS#_GPIO22
1
R1069
2

TX1M_DPB2P
TX1P_DPB2N

TX2M_DPA3P
TX2P_DPA3N

PSYNC_NEW

GPIO0
GPIO1

2
1
@ 10K_0402_5% R1068

TX1M_DPA2P
TX1P_DPA2N

DVALID

R1072
2
249_0402_1%

1
10K_0402_5%

TX0M_DPB1P
TX0P_DPB1N

AE7

<21> SOUT_GPIO8
<21> SIN_GPIO9
<21>
SCLK
<21> GPIO11
<21> GPIO12
<21> GPIO13

R1071
499_0402_1%

+VGA_VREF
1

<21>
<21>
<21>

TX0M_DPA1P
TX0P_DPA1N

AD9

R1066
2

TXCM_DPB0P
INTEGRATED
TMDS/DP PORT TXCP_DPB0N

AL7
AK7

AK4
AL3

BLM18PG121SN1D_0603

TXCM_DPA0P
TXCP_DPA0N

AK9
AL9

1U_0402_6.3V4Z
1

1
2
L96
1
BLM18PG121SN1D_0603

U5B
AJ4
AJ5

Size

Compal Electronics, Inc.

M82-S CRT/LVDS/TV-OUT
Document Number

Rev
0.1

LA-4112P
Date:

Sheet

Wednesday, November 21, 2007

1

16

of

52

U5C
Part 3 of 6
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[31..0]

<19> MDA[31..0]

+1.8VS

R1077
100_0402_1%

E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19
C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5
F5
G4
F4
B3
B2
C2
C1
E3
F3
F2
F1
G2
G1
H3
H2
K2
L3
L2
L1

C1152
0.1U_0402_16V4Z

L5
L7
J7
R1079

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
BA0
BA1
MAA12
BA2

DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7

D30
G25
C26
C21
C5
D6
D2
K3

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QS_0
QS_1
QS_2
QS_3
QS_4
QS_5
QS_6
QS_7

C30
D23
B26
B21
B6
E7
E2
J2

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
QS_7B

C31
E23
A26
A21
A6
D7
E1
J1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODT0
ODT1

E20
C11

CLK0
CLK1

A18
A11

CLKA0
CLKA1

CLK0B
CLK1B

B18
B11

CLKA0#
CLKA1#

RAS0B
RAS1B

G20
D12

RASA#0
RASA#1

CAS0B
CAS1B

D20
E12

CASA#0
CASA#1

CS0B_0
CS0B_1

E18
G18

CSA0#

CS1B_0
CS1B_1

G11
E11

CSA1#

CKE0
CKE1

D18
G12

CKEA0
CKEA1

WE0B
WE1B

D16
C10

WEA#0
WEA#1

MEMORY
INTERFACE

MVREFD
MVREFS
TEST_MCLK
TEST_YCLK
MEMTEST

DRAM_RST

4.7K_0402_5%

MAA[12..0] <19,20>
D

BA[2..0] <19,20>

DQMA#[3..0] <19>

DQMA#[7..4] <20>

QSA[3..0] <19>

QSA[7..4] <20>

QSA#[3..0] <19>

QSA#[7..4] <20>

ODTA0
ODTA1

<19>
<20>

CLKA0
CLKA1

<19>
<20>

CLKA0#
CLKA1#

<19>
<20>

RASA#0
RASA#1

<19>
<20>

CASA#0
CASA#1

<19>
<20>

CSA0#

<19>

CSA1#

<20>

CKEA0
CKEA1

<19>
<20>

WEA#0
WEA#1

<19>
<20>

J5
B

R1080
R1081
4.7K_0402_5%

4.7K_0402_5%

BA[2..0]

ODTA0
ODTA1

216-0707001-00/M82-S_BGA632

+1.8VS

MAA[12..0]

B14
A14
B13
E14
B17
A17
C15
G16
E16
C14
A12
B12
C12
D14
B15
G14

R1078
100_0402_1%

F30
F31

MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8
MA_9
MA_10
MA_11
MA_BA0
MA_BA1
MA_A12
MA_BA2

R1083
240_0402_1%

R1082
100_0402_1%

+VDD_MEM18_REFD
+VDD_MEM18_REFS

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63

write strobe read strobe

MDA[63..32]

<20> MDA[63..32]

R1084
100_0402_1%

C1153
0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S MEM

Size

Document Number

LA-4112P
Date:

ai

200810/11

Deciphered Date

Sheet

Wednesday, November 21, 2007

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

17

Rev
0.1
of

52

U5E

U5D

Part 5 of 6

PART 4 OF 6

C1158

C1161

10U_0603_6.3V6M

1U_0402_6.3V4Z
1

1U_0402_6.3V4Z
1

C1162

C1163
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
C1171
2

BLM18PG121SN1D_0603
2
1
L110
1

1
C1173

C1174

1U_0402_6.3V4Z
+1.8VS

1U_0402_6.3V4Z
1

C1172

C1164

1U_0402_6.3V4Z

C1160

10U_0603_6.3V6M

C1159

1U_0402_6.3V4Z

AC18
AC16
AC14
AC12

2
1
1U_0402_6.3V4Z 0.1U_0402_16V4Z

AF1
AF2

VDDR4
VDDR4

AE1
AE2

VDDR5
VDDR5

C1181

C1182

100mA
1

C1183

1U_0402_6.3V4Z
1
C1189

10U_0603_6.3V6M

VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT

10U_0603_6.3V6M

AA9
Y9
V9
T9
J11
J20
J21
L9

64mA

+VDD_CT

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C1190

1U_0402_6.3V4Z
1

C1191
2

VDDR3
VDDR3
VDDR3
VDDR3

PCI-Express

C1157

A15
A22
A28
A4
A8
B8
C9
D1
H1
H11
H12
H14
H16
H18
H20
H21
B31
M1

C1192
M2
M3
L4
AD11

1U_0402_6.3V4Z

NC
NC
NC
NC

P
O
W
E
R

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

VDDCI
VDDCI
VDDCI
VDDCI

J12
J14
J16
J18

Core

10U_0603_6.3V6M
1

I/O Internal

10U_0603_6.3V6M
1

2.46A

2.46A
+VDD_MEM_CLK0
+VDD_MEM_CLK1

10U_0603_6.3V6M

+1.8VS
1

1
C1203

1
C1204

C1205
2

1U_0402_6.3V4Z 1U_0402_6.3V4Z
+3.3V_DELAY

1
C1206

C1207
0.1U_0402_16V4Z

Back Bias Disable

S
2
G

SI2301BDS_SOT23

+3VS

1
C1212

R1085
100K_0402_5%

B10
B19

VSSRH
VSSRH

V11
U11

BBN
BBN

R11
P11

BBP
BBP

120mA

+VGA_CORE

VDDRH
VDDRH

1U_0402_6.3V4Z

Q170

A10
A19

C1213

2 1U_0402_6.3V4Z

Back Bias

+VGA_PCIE_VDDR

1
C1154

10U_0603_6.3V6M

C1165

2
10U_0603_6.3V6M

+VDDCI

C1175

2
2
1U_0402_6.3V4Z
220U_B2_2.5VM

C1188

2
1U_0402_6.3V4Z

C1196

2
2
1U_0402_6.3V4Z

+VGA_CORE

1U_0402_6.3V4Z
1
1

C1197

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
1

C1199

15A
1
C1180

C1187

C1195

1U_0402_6.3V4Z
1
C1198

C1170

C1179

2
2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
1

C1194

C1169

1U_0402_6.3V4Z
1
1

C1186

1U_0402_6.3V4Z
1

BLM18PG121SN1D_0603
1
2
+1.1VS
L109
1

2
2 1U_0402_6.3V4Z
1U_0402_6.3V4Z

2
2
1U_0402_6.3V4Z

C1185

C1193
2
10U_0603_6.3V6M

C1168

C1178

1U_0402_6.3V4Z
1

2
10U_0603_6.3V6M

C1177
2

1.36A

1
C1167

+1.8VS

2 0.1U_0402_16V4Z

2
2
1U_0402_6.3V4Z

C1184

1U_0402_6.3V4Z
1

2
10U_0603_6.3V6M

BLM18PG121SN1D_0603
1
2
L108
C1156
0.5A

0.1U_0402_16V4Z

C1166

C1176

C1155

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
+VGA_PCIE_VDDC
1
1

2
2
10U_0603_6.3V6M

C1200

C1201

2
2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
1
1
C1208
C1209
C1210

C1202

2
1U_0402_6.3V4Z

BLM18PG121SN1D_0603
2
1
L111
C1211

2
1U_0402_6.3V4Z

2
10U_0603_6.3V6M

216-0707001-00/M82-S_BGA632

1U_0402_6.3V4Z
1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

Memory
I/O
Clock

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PCI-Express GND

A13
A2
C18
A24
A30
AA1
AA11
AA14
AA17
AA20
AA6
AC2
AC7
AE3
AL4
AD14
AF12
AF14
AD16
AD18
AE6
AG2
AE9
AH25
AK1
AK31
AJ6
AL2
AL30
B1
C13

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

+1.8VS

Memory I/O

AA26
AA29
AC26
AD31
AE29
AE30
AE31
F28
G26
G29
G30
G31
H29
J25
J26
L26
L29
L30
L31
M26
M29
P26
R29
R30
R31
T26
U29
V26
Y26
Y29
Y30
Y31

CORE GND
B

R1086
2
1
@ 330K_0402_5%
1
2
R1087 0_0402_5%

1.1VS_POK
1
R1088

2
4.7K_0402_5%

D
Q171

2
G
3

<43,49> SUSP

+3VS

216-0707001-00/M82-S_BGA632

0.01U_0402_25V7K

2N7002_SOT23-3

C1214

+1.8VS

+VDD_MEM_CLK0
2

1
L112
BLM18PG121SN1D_0603
C1215

2
1

2
1U_0402_6.3V4Z

10U_0603_6.3V6M

1.1A

C1216

C1217

0.1U_0402_16V4Z

+VDD_MEM_CLK1
2
1
L113
BLM18PG121SN1D_0603
C1218

1
C1219

10U_0603_6.3V6M

1.1A

Compal Secret Data

Security Classification

1
0.1U_0402_16V4Z

1U_0402_6.3V4Z

2
C1220

Issued Date

2007/10/11

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

M82-S POWER

Size

Document Number

Rev
0.1

LA-4112P
Date:

Wednesday, November 21, 2007

1

Sheet

18

of

52

L8

CS

WEA#0

K3

WE

RASA#0

K7

RAS

CASA#0

L7

CAS

DQMA#2
DQMA#0

F3
B3

LDM
UDM

K9

ODT

QSA2
QSA#2

F7
E8

LDQS
LDQS

R1089
4.99K_0402_1%

QSA0
QSA#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

R1091
4.99K_0402_1%

C1225
0.1U_0402_16V4Z

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

+1.8VS

0.1U_0402_16V4Z
1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

K8
J8

CK
CK

CKEA0

K2

CKE

CSA0#

L8

CS

WEA#0

K3

WE

RASA#0

K7

RAS

CASA#0

L7

CAS

DQMA#1
DQMA#3

F3
B3

LDM
UDM

ODTA0

K9

ODT

QSA1
QSA#1

F7
E8

LDQS
LDQS

QSA3
QSA#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

C1222
2 1U_0402_6.3V4Z
+1.8VS

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

+1.8VS
1

+VRAM_REF1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

C1221

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

BA0
BA1

R1090
4.99K_0402_1%

+VRAM_REF2

R1092
4.99K_0402_1%

C1226
0.1U_0402_16V4Z

HYB18T256161BF-25
@

MDA29
MDA27
MDA31
MDA24
MDA26
MDA28
MDA25
MDA30
MDA14
MDA9
MDA12
MDA8
MDA10
MDA15
MDA11
MDA13

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

QSA#[7..0]

<17,20> QSA#[7..0]

DQMA#[7..0]

<17,20> DQMA#[7..0]

MAA[12..0]

<17,20> MAA[12..0]

MDA[63..0]

<17,20> MDA[63..0]

<17>

ODTA0

<17>

CKEA0

<17>

RASA#0

<17>

CASA#0

<17>

WEA#0

<17>

CSA0#

ODTA0
CKEA0
RASA#0

+1.8VS

0.1U_0402_16V4Z
1

CASA#0
WEA#0
CSA0#

+1.8VS
1
C1224

2
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

QSA[7..0]

<17,20> QSA[7..0]

C1223

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

BA[2..0]

<17,20> BA[2..0]

2 1U_0402_6.3V4Z

<17>

CLKA0

<17>

CLKA0#

CLKA0
CLKA0#
1

CKE

CSA0#

ODTA0
+1.8VS

CK
CK

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

K2

L2
L3

R1093
56_0402_5%

R1094
56_0402_5%

HYB18T256161BF-25
@

K8
J8

CKEA0

BA0
BA1

CLKA0#
CLKA0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

MDA1
MDA6
MDA3
MDA4
MDA5
MDA0
MDA7
MDA2
MDA19
MDA21
MDA16
MDA22
MDA23
MDA17
MDA20
MDA18

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

U7

BA0
BA1

L2
L3

U6
BA0
BA1

SA00002A200(HYNIX) S IC 16M16/500 HY5PS561621BFP-2L FBGA 84P 1.8V

C1227
470P_0402_50V7K

SA00002A500(QIMONDA) S IC D2 16M16/500 HYB18T256161BF-20 84P

SA00000S810(QIMONDA) S IC D2 16M16/400 HYB18T256161BF-25 84P

+1.8VS
+1.8VS
10U_0603_6.3V6M
1
B

C1229

1
C1230

0.1U_0402_16V4Z
1

C1231
2

1
C1232

0.1U_0402_16V4Z
1

C1233
2

1
C1234

1
C1235

0.01U_0402_16V7K
1
1
+
C1228
220U_6.3VM_R15
C1236

10U_0603_6.3V6M
1
C1237

C1238
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C1239
2

1
C1240

0.1U_0402_16V4Z
1

C1241
2

0.01U_0402_16V7K

C1242
2

C1243
2

C1244
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S VRAM

Size

Document Number

LA-4112P
Date:

ai

200810/11

Deciphered Date

Wednesday, November 21, 2007

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

Sheet

19

Rev
0.1
of

52

U8
BA0
BA1

L2
L3

U9

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDA36
MDA35
MDA39
MDA32
MDA33
MDA38
MDA34
MDA37
MDA45
MDA43
MDA46
MDA40
MDA41
MDA44
MDA42
MDA47

BA0
BA1

L2
L3

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDA58
MDA59
MDA61
MDA56
MDA63
MDA62
MDA57
MDA60
MDA50
MDA53
MDA48
MDA55
MDA52
MDA49
MDA54
MDA51

BA[2..0]

<17,19> BA[2..0]

DQMA#[7..0]

<17,19> DQMA#[7..0]

MAA[12..0]

<17,19> MAA[12..0]

QSA#[7..0]

<17,19> QSA#[7..0]

QSA[7..0]

<17,19> QSA[7..0]

MDA[63..0]

<17,19> MDA[63..0]

ODTA1

<17> ODTA1

CSA1#

L8

CKE

CS

WEA#1

K3

WE

RASA#1

K7

RAS

CASA#1

L7

CAS

F3
B3

LDM
UDM

DQMA#5
DQMA#4
ODTA1

K9

ODT

QSA5
QSA#5

F7
E8

LDQS
LDQS

QSA4
QSA#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

CKEA1

CSA1#

C1249
0.1U_0402_16V4Z

RASA#1

K7

RAS

CASA#1

L7

CAS

F3
B3

LDM
UDM

K9

ODT

QSA6
QSA#6

F7
E8

LDQS
LDQS

QSA7
QSA#7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8VS
1

ODTA1

2 1U_0402_6.3V4Z

R1096
4.99K_0402_1%

+VRAM_REF4

R1098
4.99K_0402_1%

C1250
0.1U_0402_16V4Z

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

CSA1#

<17> CSA1#

0.1U_0402_16V4Z
1

+1.8VS
1
C1248
2 1U_0402_6.3V4Z

<17>

CLKA1

<17>

CLKA1#

CLKA1
CLKA1#
R1099
56_0402_5%

HYB18T256161BF-25
@

R1100
56_0402_5%
2

HYB18T256161BF-25
@

WEA#1

<17> WEA#1

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

CASA#1

<17> CASA#1

C1247

+1.8VS

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

C1245

RASA#1

<17> RASA#1

WE

+VRAM_REF3
1

R1097
4.99K_0402_1%

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

CS

K3

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

CKE

WEA#1

C1246

R1095
4.99K_0402_1%

L8

DQMA#6
DQMA#7
0.1U_0402_16V4Z
1

+1.8VS

K2

CKEA1

<17> CKEA1

K2

+1.8VS

CKEA1

+1.8VS

2
+1.8VS

+1.8VS
10U_0603_6.3V6M
1

C1251
470P_0402_50V7K

C1252

1
C1253

0.1U_0402_16V4Z
1

C1254

1
C1255

0.1U_0402_16V4Z
1

C1256
2

1
C1257

0.01U_0402_16V7K
1

C1258
2

10U_0603_6.3V6M

1
C1259

1
C1260

10U_0603_6.3V6M

1
C1261

0.1U_0402_16V4Z
1

C1262
2

1
C1263

0.1U_0402_16V4Z
1

C1264
2

0.01U_0402_16V7K

C1265
2

C1266
2

C1267
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2007/10/11

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S VRAM

Size

Document Number

Rev
0.1

LA-4112P
Date:

Wednesday, November 21, 2007

1

Sheet

20

of

52

+3.3V_DELAY

10K_0402_5%2

@
1 R1101
@
1 R1102

10K_0402_5%2

@
1 R1103

10K_0402_5%2

@
1 R1104

10K_0402_5%2

@
1 R1105

10K_0402_5%2

SOUT_GPIO8
1 R1106

SOUT_GPIO8 <16>

10K_0402_5%2

@
1 R1107 SIN_GPIO9

SIN_GPIO9 <16>

10K_0402_5%2

GPIO0

<16>

GPIO1

<16>

GPIO4

<16>

TX_PWRS_ENB

GPIO0

GPIO5

<16>

TX_DEEMPH_EN

GPIO1

GPIO6

<16>

BIF_DEBUG_ACCESS

GPIO4

DEBUG SIGNALS MUXED OUT

BIF_GEN2_EN_A

GPIO5

PCI-E 5.0GT/s or 2.5 GT/s select

DEBUG_ I2C_ENABLE

GPIO6

Internal use only

STRAPS

GPIO9 = 0 (BIOS_ROM_EN = 0)
10K_0402_5%2

10K_0402_5%2

1 R1108
@
1 R1109
@
1 R1110

10K_0402_5%2

@
1 R1111 SCS#_GPIO22

10K_0402_5%1

@
2 R1112

10K_0402_5%2

10K_0402_5%2

GPIO11

<16>

GPIO12

<16>

GPIO13

<16>

GPIO[13:11]

0
0
0
1

0
0
1
0

MEMORY SIZE
256MB

GPIO8

ROMIDCFG[3:0]

GPIO
[9,13,12,11]

ENABLE HD AUDIO(M8X)
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

BIOS_ROM EN

GPIO_22_ROMCSB

BIF_VGA_DIS
BIF_HDMI_EN

0 1 0 1

DISABLE EXTERNAL BIOS ROM

PSYNC

VGA ENABLED===0 is enable

HSYNC

HDMI ENABLE

64MB
512MB

PSYNC <16>

1 R1113

PCIE FULL TX OUTPUT SWING

PCIE TRANSMITTER DE-EMPHASIS ENABLES

BIF_AUDIO_EN

128MB

0
1
0
0

RECOMMENDED
M8X

DESCRIPTION OF RECOMMENDED SETTING

PIN

VRAM_ID 3 ,2 ,1 ,0

CRT_HSYNC <14,16,23>

10K_0402_5%
2
1
@ R1114

400MHz
DVPDATA
(23,22,21,20)

+1.8VS
VRAM_ID0 <16>

1
2
R1116
10K_0402_5%
10K_0402_5%
2
1
+1.8VS
@ R1117

0 0 0 0

Samsung 32Mx16 1.8V

0 0 0 1

Hynix 16Mx16 1.8V

0 0 1 0

Hynix 32Mx16 1.8V

0 0 1 1

Qimonda 32Mx16 1.8V

0 1 0 0

Qimonda 32Mx16 1.8V

0 0 0 0

Samsung 32Mx16 1.8V

0 0 0 1

DB VRAM status

VRAM_ID[3:0]

VRAM_ID1 <16>
500MHz
DVPDATA
(23,22,21,20)

1
2
R1119
10K_0402_5%
10K_0402_5%
2
1
+1.8VS
R1120
VRAM_ID2 <16>
1
2
R1122 @ 10K_0402_5%
10K_0402_5%
2
1
+1.8VS
@ R1123

Hynix 16Mx16 1.8V

0 0 1 0

Qimonda 16Mx16 1.8V

0 0 1 1

Samsung 16Mx16 1.8V

0 1 0 0

400MHz
DVPDATA
(23,22,21,20)

Qimonda 32Mx16 1.8V

0 1 0 0

500MHz
DVPDATA
(23,22,21,20)

Hynix 32Mx16 1.8V

0 1 1 0

default
Options

ATI RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESE

VRAM_ID3 <16>
1
R1125

Samsung 16Mx16 1.8V

2
10K_0402_5%
GPIO2

GPIO3

GPIO5

GPIO6

DVALID

H2SYNC

V2SYNC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
GENERICC

GPIO21_BB_EN

GPIO_28_TDO

FLASH ROM

VGA Thermal Sensor ADM1032ARMZ

Closed to U80

+3VS

U11
SIN_GPIO9

C1268
0.1U_0402_16V4Z

<16>

HOLD

10K_0402_5%

VCC

+3.3V_DELAY

VDD

SCLK

SMB_EC_CK2 <6,40>

D+

SDATA

SMB_EC_DA2 <6,40>

D-

ALERT#

THERM#

GND

1
@ RV1

C1269
1
2
2200P_0402_50V7K

@ M25P10-AVMN6T_SO8~D

om
Compal Secret Data

Security Classification
Issued Date

ai

l.c

2
4.7K_0402_5%

2007/10/11

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

nf
@
ho
tm

1
R1126

VSS

SOUT_GPIO8

ADM1032ARMZ REEL_MSOP8
+3.3V_DELAY

@
RV2
10K_0402_5%

<16> THM_ALERT#

M82-S Filters / Strap

Size

Document Number

LA-4112P
Date:

ai

D-

Wednesday, November 21, 2007

he
x

<16>

D+

SCLK

SCLK

<16> SCS#_GPIO22
1
U12

<16>

Sheet

21

Rev
0.1
of

52

+1.2V_HT >150mil
+VDDCLK_IO >15mil

0.1U_0402_16V4Z
1
C452

10U_0805_10V4Z

C453
2

0.1U_0402_16V4Z
1

C454

+3VS_CLK >15mil

C456

R167

0.1U_0402_16V4Z
1

C455

2
0.1U_0402_16V4Z

10_0805_5%2

R168
1
2
0_0805_5%

+3VS_CLK

+3VS

+3VS >150mil
+VDDCLK_IO

+1.2V_HT

C457

2
0.1U_0402_16V4Z

1
C444
10U_0805_10V4Z

C445
0.1U_0402_16V4Z

C446
0.1U_0402_16V4Z

C447
0.1U_0402_16V4Z

C448
0.1U_0402_16V4Z

C449
0.1U_0402_16V4Z

1
@ C451

C450
0.1U_0402_16V4Z

1U_0402_6.3V4Z

2
1

C458

C459

C460

C461

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

EMI Caps for single end clock.

CLK_48M_USB

22P_0402_50V8J
2

22P_0402_50V8J

GND

U10

<8,9,27,37> SMB_CK_CLK0
<8,9,27,37> SMB_CK_DAT0
<16>
<16>

27M_CLK
27M_SSC

R1055
R1056

1
1

+3VS_CLK
33_0402_5%
2
33_0402_5%
2

<11> CLK_SBLINK_BCLK#
<11> CLK_SBLINK_BCLK

SB LINK

+VDDCLK_IO

MiniCard_1(delete)
MiniCard_2

<33> CLK_PCIE_MCARD2#
<33> CLK_PCIE_MCARD2

1
R946
CLK_CPU_BCLK#_R 1
R945

SEL_SATA

VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO

@ C1076
5P_0402_50V8C

2
0_0402_1%
2
0_0402_1%

R186
@ 261_0402_1%

CPU

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

+3VS_CLK
+VDDCLK_IO
CLKREQ_NCARD#
CLKREQ_MCARD2#

CLKREQ_MCARD2# <33>

+3VS_CLK

CLK_SBSRC_BCLK <26>
CLK_SBSRC_BCLK# <26>
+3VS_CLK
CLKREQ_MCARD1#
CLKREQ4
1
2
R372
10K_0402_5%

+3VS_CLK

SB SRC

For ICS need to pull high.

For SLG is NC

+3VS_CLK
+VDDCLK_IO
3

SLG8SP626VTR_QFN72_10x10

S
S
S
S

IC
IC
IC
IC

NBGFX_CLK <11>
NBGFX_CLK# <11>

1
R324
1
R325
CLKREQ_MCARD1#
1
R326
CLKREQ_LAN#
1
R1039
CLKREQ4
1
@ R1045

SLG8SP626VTR YA QFN 72P CLK GEN

SLG8SP626VTR QFN 72P CLK GEN(XA)
RTM880N-795-GRT QFN 72P CLK GEN
ICS9LPRS476BKLFT MLF 72P CLK GEN

CLK_PCIE_MCARD0 <34>
CLK_PCIE_MCARD0# <34>
CLKREQ_LAN# <32>
CLK_PCIE_LAN <32>
CLK_PCIE_LAN# <32>

chip(Dis)

NB CLOCK INPUT TABLE

LAN
New Card(delete)

SEL_SATA
0

* default

RS780

100M DIFF
100M DIFF

100M DIFF
100M DIFF

REFCLK_N

14M SE (1.8V)
NC

14M SE (1.1V)
vref

GFX_REFCLK

100M DIFF

100M DIFF(IN/OUT)*

REFCLK_P

configure as 27M and 27M_SS output

27M_SEL
configure as normal SRC(SRC_6) output

RX780

HT_REFCLKP
HT_REFCLKN

1 *

+3VS_CLK

Card Reader

NB CLOCKS
27M_SEL

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

CLKREQ_MCARD2#

NB GFX

CLK_PCIE_VGA <15>
CLK_PCIE_VGA# <15>VGA

CLKREQ_LAN#

configure as SATA output

1
4

CLK_CPU_BCLK <6>

CLKREQ_NCARD# , CLKREQ_LAN# , CLKREQ4 ,

CLKREQ_MCARD2#=width
/spacing/Others=8mil/8mil/12mil

R180
8.2K_0402_5%
1

R181
8.2K_0402_5%

@ C1074
5P_0402_50V8C
2
@ C1075
2 5P_0402_50V8C
1

CLK_CPU_BCLK# <6>

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

CLK_14M_SIO

CLKREQ_NCARD#

2
1

1.1V 200R/100R
1

2
+3VS_CLK
8.2K_0402_5%

SA00001Z300
SA00001Z310
SA000025B00
SA00001ZV10

@ R179
8.2K_0402_5%

1.8V 75R/100R

RS780

CLK_14M_SIO <39>
CLK_NBHT <11>
CLK_NBHT# <11> NB

CLK_CPU_BCLK_R

SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO

+3VS_CLK

RX780

1
R174

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

2
100_0402_1%

R220 33_0402_5%
1
2

VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC

+3VS_CLK
+VDDCLK_IO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

CLK_XTAL_OUT
CLK_XTAL_IN

14.31818MHZ_20P_6X1430004201
1
C465

NB_OSC_14.318M <11>
1
R380

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

2
200_0402_1%

NB_OSC_14.318M

OSC_14M_NB

CLK_48M_USB <27>

VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#

C464

73

CLK_48M_USB_R

Y2

NB_OSC_14.318M_R
SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK

CLK_XTAL_IN

R379

+3VS_CLK

CLK_XTAL_OUT

33_0402_5%

R170 1

CLK_XTAL_IN/OUT=width
/spacing/Others=10mil/10mil/20mil

configure as SRC_7 output

* default

Use voltage divider resistor R379 & R380 to pull low

1

2007/10/11

Issued Date

0*
configure as differential 100MHz output
* default

Compal Secret Data

Security Classification

configure as single-ended 66MHz output

NB_OSC_14.318M

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

Compal Electronics, Inc.

Clock generator

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

22

of

52

CRT CONNECTOR

+5VS

+R_CRT_VCC

@ D35

@ D37

@ D34

+CRT_VCC
F2

D36

2
1

RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z

+5VS

DAN217_SC59DAN217_SC59

DAN217_SC59

JCRT

+3.3V_DELAY

1
C471
2

1
C859
2

1
C469
2

C858

HSYNC
BLUE_L

1
C476
2

1
C472
2

22P_0402_50V8J

R217

D_DDCDATA
GREEN_L

22P_0402_50V8J

R211

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED_L

22P_0402_50V8J

R214

6P_0402_50V8K

BLUE
6P_0402_50V8K

BLUE

6P_0402_50V8K

<16>

GREEN

2
1
150_0402_1%

GREEN

2
1
150_0402_1%

RED

<16>

2
1
150_0402_1%

<16>

L47
1
2
BLM15AG121SN1D_0402
L48
1
2
BLM15AG121SN1D_0402
L49
1
2
BLM15AG121SN1D_0402

RED

+CRT_VCC

VSYNC
D_DDCCLK

16
17
2

CONN@ SUYIN_070546FR015S263ZR

+3VS
+CRT_VCC

R218
2.2K_0402_5%
<14,16,21> CRT_HSYNC

1
1

5
1

R100
2.2K_0402_5%

D_DDCDATA

D_HSYNC

L84
1

0_0603_5%
2

HSYNC

U14
SN74AHCT1G125GW_SOT353-5

Q10A
2N7002DW-7-F_SOT363-6

<16> VGA_DDC_DAT

1
2
C473
0.1U_0402_16V4Z

P
OE#

R238
4.7K_0402_5%

+CRT_VCC

R237
4.7K_0402_5%

2 470P_0402_50V8J

D_ VSYNC

L83
1

0_0603_5%
2

VSYNC

U13
SN74AHCT1G125GW_SOT353-5

1
@ C474

@ C470

10P_0402_50V8J

<14,16> CRT_VSYNC

@ C856

470P_0402_50V8J

1
2
@ C477
0.1U_0402_16V4Z
2 A

10P_0402_50V8J

@ C857

P
OE#

5
1

D_DDCCLK

4
3
Q10B
2N7002DW-7-F_SOT363-6

<16> VGA_DDC_CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

CRT Connector

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

23

of

Rev
0.1
52

+5VALW
1

WebCam+Digital Mic

DMICCLK
DMICDAT

1
2
3
4
5
6

G2

USB20N5

VIN

IO1

IO2 GND

GND

1
VOUT

BP

@ R891

1U_0603_10V6K

EN

C719
1

RT9193-39GB_SOT23-5

C720

R1013

10U_0805_10V4Z
1
C1270
0.01U_0402_25V4Z

0_0402_5%
2

@ R1014
1
2
0_0402_5%

CAM_SHDN <28>

High active

USB_VCCA is +3.9V, R892:100K; R891:215KKohm

G916 Vref=1.25V

D52
+USB_CAM

2
3
G1

ACES_88231-06001
CONN@

VIN

+USB_CAM

1
2
3
4
5
6

JP7
USB20P5
USB20N5

10U_0805_10V4Z

U54

PJP4
PAD-OPEN 2x2m

@ C1072

+USB_CAM
215K_0402_1%

USB20P5

D22
+USB_CAM

@ PRTR5V0U2X_SOT143-4

USB20_N5

Close to JP7

VIN

IO1

IO2 GND

USB20_P5

@ PRTR5V0U2X_SOT143-4

1
2

+LCDVDD
1

C487
4.7U_0805_10V4Z

C491
0.1U_0402_16V4Z

Q45B
2N7002DW-7-F_SOT363-6

80mil

JLVDS

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+

LVDS_A2- <16>
LVDS_A2+ <16>
LVDS_A1- <16>
LVDS_A1+ <16>
LVDS_A0- <16>
LVDS_A0+ <16>
LVDS_ACLK- <16>
LVDS_ACLK+ <16>

DMIC_DAT
DMIC_CLK

DMIC_DAT <35>
DMIC_CLK <35>
1
2
@ R491 470_0805_5%

INV_PWM
BKOFF#
DAC_BRIG
LCD_DDC_CLK
LCD_DDC_DAT

ACES_88242-4001
CONN@

9/20 SP02000EA00/SP02000BW00

+5VS
Logo BackLight
INV_PWM <40>
BKOFF#
<40>
DAC_BRIG <40>

+USB_CAM

+3VS

LCD_DDC_CLK <16>
LCD_DDC_DAT <16>

C483
680P_0402_50V7K

LVDS_BCLK+
LVDS_BCLK-

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

C482
680P_0402_50V7K

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

USB20_P5
USB20_N5

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

C867
680P_0402_50V7K
2
1

680P_0402_50V7K

USB20_P5
USB20_N5

<16> LVDS_BCLK+
<16> LVDS_BCLK<16>
<16>
<16>
<16>
<16>
<16>

1000P_0402_50V7K

LVDS CONN

680P_0402_50V7K

C866
680P_0402_50V7K
2
1

C481

+3VS

C863

C480

<27>
<27>

C479
680P_0402_50V7K

R276
2.2K_0402_5%

Q43
SI2301BDS-T1-E3_SOT23-3

<16> VGA_ENVDD

80mil
R222
1
2
100K_0402_5%

B+
L44
1
2
FBMA-L11-201209-221LMA30T_0805

+3VS

6 2

R224
1M_0402_5%

Q45A
2N7002DW-7-F_SOT363-6

INVPWR_B+

0_0402_5%
2 DMICDAT
2 DMICCLK
0_0402_5%

+5VALW

R225
470_0805_5%

+LCDVDD

@ R1029
DMIC_DAT1
DMIC_CLK1
@ R1030

0_0402_5%
2 USB20P5
2 USB20N5
0_0402_5%

Close to JLVDS

Close to JLVDS

+LCDVDD

@ R1027
USB20_P5 1
USB20_N51
@ R1028

2 @

BKOFF#
1
4.7K_0402_5%

2
@ R483

LCD_DDC_CLK 1
4.7K_0402_5%

2
R274

LCD_DDC_DAT 1
4.7K_0402_5%

2
R275

+3.3V_DELAY

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

LCD CONN. / WebCam

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

24

of

52

+3VS

R176
4.7K_0402_5%

HDMI_HPD

2.2K_0402_5%
Y

HPD

R628
100K_0402_5%
<16>

U39
SN74AHCT1G125GW_SOT353-5

C850
0.1U_0402_16V4Z

HDMI_SDATA

HDMI_SCLK

4
3
Q134B
2N7002DW-7-F_SOT363-6

<16> HDMICLK_VGA

+3VS

R236
6.8K_0402_5%

5
1
1

P
OE#

0.1U_0402_16V4Z

1
R615

R210
6.8K_0402_5%

1
6
Q134A
2N7002DW-7-F_SOT363-6

<16> HDMIDAT_VGA

2
2

+HDMI_5V_OUT

C851

R209
4.7K_0402_5%
2

+HDMI_5V_OUT

+3.3V_DELAY

C:Chg. PN to SB770020010.

MP:Update D10 to meet HDMI.

D10
+5VS

+HDMI_5V_OUT

RB491D_SOT23
1

<16> TMDS_B_CLK#
<16> TMDS_B_CLK

C507 1
C508 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

<16> TMDS_B_DATA0#
<16> TMDS_B_DATA0

C655 1
C675 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+

<16> TMDS_B_DATA1#
<16> TMDS_B_DATA1

C804 1
C827 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+

C852 1
C853 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX2HDMI_TX2+

<16> TMDS_B_DATA2#
<16> TMDS_B_DATA2

0.1U_0402_16V4Z

HDMI Connector
COMMON MODE CHOCK is SM070000K00 KING_WCM-2012-900T_4P

HDMI_CLKHDMI_CLK+

HDMI_TX0HDMI_TX0+

HDMI_TX1HDMI_TX1+

HDMI_TX2HDMI_TX2+

HDMI_CLK+

2
2

+5VS

R141
499_0402_1%

UMA use 750 ohm

VGA use 499 ohm

HDMI_TX0+
HDMI_TX0-

1
1

R139
499_0402_1%

+5VS

2
2

R304
499_0402_1%

1
1

2
2

R172
499_0402_1%
R297
499_0402_1%

+5VS
6

+5VS

R173
499_0402_1%

1
1

1
1

R307
499_0402_1%

HDMI_TX1+

2
2

HDMI_CLKR315
499_0402_1%

C468

HDMI_TX1HDMI_TX2+

HDMI_TX24

Q136A
Q162A
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
Q136B
Q162B
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6

1
R1132
1
R1133

2
0_0402_5%
2
0_0402_5%

HDMI_R_CK+

1
R1134
1
R1135

2
0_0402_5%
2
0_0402_5%

HDMI_R_D0+

1
R1136
1
R1137

2
0_0402_5%
2
0_0402_5%

HDMI_R_D1+

1
R1138
1
R1139

2
0_0402_5%
2
0_0402_5%

HDMI_R_D2+

HDMI_R_CK-

JHDMI
+HDMI_5V_OUT

HDMI_R_D0-

HDMI_R_D1-

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

18
16
15
19

+5V
SDA
SCL
HP_DET

HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

12
10
9
7
6
4
3
1

CKCK+
D0D0+
D1D1+
D2D2+

CEC
Reserved

13
14

GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

2
5
8
11
20
21
22
23
17

CONN@ SUYIN_100042MR019S153ZL
HDMI_R_D2-

9/20 DC020709040

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

HDMI

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

25

of

Rev
0.1
52

U15A
N2

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

PCIE_CALRP
PCIE_CALRN

T25
T24

PCIE_CALRP
PCIE_CALRN

+SB_PCIEVDD

P24

PCIE_PVDD

P25

PCIE_PVSS

@ NC7SZ08P5X_NL_SC70-5

1
0_0402_5%

<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

C492
C493
C494
C495
C496
C497
C498
C499

R305
2

PCIE_CALRP=W/S=4/8(55ohm impedance), <1"

+PCIE_VDDR

PCIE_CALRN=W/S=4/8(55ohm impedance), <1"

+1.2V_HT

L53

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

562_0402_1%
1
2 R306
1
2.05K_0402_1%

1
2
BLM18PG121SN1D_0603
C504
10U_0805_10V4Z

SB700

NB_RST#_R

C505
1U_0402_6.3V4Z

A_RST#

Part 1 of 5

@ R314 20M_0402_5%
1
2
C643
SB_32KHI

18P_0402_50V8J

Y3

R389
20M_0603_5%

NC

IN

NC

SB_32KHI/HO=W/S=4/20(55ohm
impedance), <1.5"

K23
K22

NB_DISP_CLKP
NB_DISP_CLKN

M24
M25

NB_HT_CLKP
NB_HT_CLKN

P17
M18

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

J19
J18

GPP_CLK0P
GPP_CLK0N

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

PCI INTERFACE

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

32.768KHZ_12.5PF_1TJS125BJ4A421P

C652

OUT

N25
N24

CLOCK GENERATOR

SB_32KHO

J20

P4
P3
P1
P2
T4
T3

PCIRST#

N1

25M_X2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

1 CPU_LDT_REQ#
10K_0402_5%

+3VS

2
@ R319

H_PROCHOT#
1
10K_0402_5%
<6,11> CPU_LDT_REQ#
<6> H_PROCHOT#

SB_32KHO

B3

X2

CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD

F23
F24
F22
G25
G24

CLK_PCI_SIO_R

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
RTCCLK
INTRUDER_ALERT#
VBAT

+3VALW
+1.8V
2

CLK_PCI_SIO2 <39>

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

<30>
<30>
<30>
<30>
<30>
<30>

PCI_SERR# <40>

PAD

T15

PAD
PAD

T16
T17

PCI_PIRQH#

R967

1 0_0402_5%

C3
C2
B2

<39,40>

RTC_CLK <30>
+SB_VBAT

SA00001S510(A11) S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

STRAP PIN

C509

+RTCVCC_R
R316
120_0402_5%
1
2

C510
2

2
1U_0402_6.3V4Z

+RTCVCC

R317
120_0402_5%
1
2

4.7K_0402_5%

D42
2

R876
3
1
2
W=20mils
1K_0402_5%
DAN202U_SC70

JBATT1
W=20mils

J1
@ JUMP_43X39

H_PWRGD

1
2
3
4

1
2
GND
GND

CONN@ ACES_85205-02001
+RTCBATT_R

9/20 SP020008T00

0.1U_0402_16V4Z

+RTCBATT

1
1
1

PCB-MB
DA80000AC00 LA-4112P

+3VL

+SB_VBAT

C509 place close

to U15.b2, <0.5".

@ Q155
FDV301N_NL_SOT23-3

2
R1161

+SB_VBAT/+RTCVCC_R/+RTCVCC/+RTCBATT_R/+RTCBATT=W/S=25/20(55ohm impedance)

1
0_0402_5%

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

ZZZ

LPC_DRQ# <39>
SIRQ

G
3

CLK_PCI_EC <30,40>

STRAP PIN
EC & Debug

SA00001S560(A12) S IC 218S7EALA12FG SB700 BGA 528P SB 0FH

<6> H_PWRGD_CPU

ACCEL_INT <37>

22_0402_5%
CLK_PCI_EC_RR302 1
CLK_PCI_EC
2
LPCCLK1 <30>
LPC_AD0 <39,40>
LPC_AD1 <39,40>
LPC_AD2 <39,40>
LPC_AD3 <39,40>
LPC_FRAME# <39,40>

@ R986

PCICLK2 <30>
CLK_PCI_SIO <30,39>
PCI_CLK4 <30>
PCI_CLK5 <30>

2 22_0402_5%

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

218S7EALA11FG_BGA528_SB700

2
@ 22_0402_5%

R301 1

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

RTC

<6,11> LDT_STOP#
<6>
LDT_RST#

X1

L PC

2
@ R318

A3

CPU

+1.8VS

SB_32KHI

RTC XTAL

18P_0402_50V8J

Close to SB

1
R1173

Close to SB

<22> CLK_SBSRC_BCLK
<22> CLK_SBSRC_BCLK#

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

2
R312

2 NB_RST#_R
@ 8.2K_0402_5%

1
R300

PLT_RST# <11,14,15,32,33,34,39,40>

PCI CLKS

4PLT_RST#

U16

PCI EXPRESS INTERFACE

NB_RST#_R

Check AMD need pull low or not

@ 0.1U_0402_16V4Z
2

+3VALW

C506

Title

Compal Electronics, Inc.

SB700-PCIE/PCI/ACPI/LPC/RTC

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

26

of

52

@R1053 2
100_0402_5%

1
U15D

+3VS
2
4.7K_0402_5%

SUS_STAT#

+3VALW

<6,40> H_THERMTRIP#
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%

SB_TEST2

EC_RSMRST#

<40> EC_RSMRST#

SB_TEST1

SB700 has internal PD

SB_TEST0

R327
2.2K_0402_5%

+3VS
R328

2 2.2K_0402_5%

SMB_CK_CLK0

R329

2 2.2K_0402_5%

SMB_CK_DAT0

D3

1
R320
1
R321
1
R322

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

SB_SPKR=W/S=4/4(55ohm impedance)
<8,9,22,37>
<8,9,22,37>
<33>
<33>

+3VALW
R331

2 2.2K_0402_5%

SMB_CK_CLK1

R332

2 2.2K_0402_5%

SMB_CK_DAT1

<35> SB_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

+3VS

<40> EC_LID_OUT#
1
2
R1147 100K_0402_5%
33_0402_5%
1
2
33_0402_5%
1
2
33_0402_5%
1
2
33_0402_5%
1
2

+3VS
<35>
<41>
<41>
<35>
<35>
<41>

HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDIN0
HDA_SDIN1

<41> HDA_SYNC_MDC
<35> HDA_SYNC_CODEC
<35> HDA_RST#_CODEC
<41> HDA_RST#_MDC

<30,40> HDARST#

R333
R334
R335
R336

R337
R338

33_0402_5%
33_0402_5%

1
1

2
2

R339
R340

33_0402_5%
33_0402_5%

1
1

2
2

@ R83

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

2
10K_0402_5%

EXP_CPPE#
<34>

CR_CPPE#

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SYNC
HDARST#

AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5

B9
B8
A8
A9
E5
F8
E4

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

M1
M2
J7
J8
L8
M3
L6
M4
L5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

PAD T41

STRAP PIN

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

USB MISC

2
R323

E6
E7

USB_FSD12P
USB_FSD12N

F7
E8

USB_HSD11P
USB_HSD11N

H11
J10

USB-11 New Card(delete)

USB_HSD10P
USB_HSD10N

E11
F11

USB-10 MiniCard(TV)(delete)

USB_HSD9P
USB_HSD9N

A11
B11

USB_HSD8P
USB_HSD8N

C10
D10

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

G11
H12

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

E12
E14

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

C12
D12

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B12
A12

USB_HSD3P
USB_HSD3N

G12
G14

USB_HSD2P
USB_HSD2N

H14
H15

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

A13
B13

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

B14
A14

USB20_P0
USB20_N0

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

RSMRST#

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

CLK_48M_USB <22>
USB_RCOMP 1
11.8K_0402_1%

USB_FSD13P
USB_FSD13N

USB 1.1

<40>
<40>
<40>
<40>

2@ 100P_0402_25V8K

USB_RCOMP=W/S=9/20(35ohm impedance), <1"

USB 2.0

1
0_0402_5%

GPIO

2
@ R994

ACPI / WAKE UP EVENTS

<33> MINI_PCIE_WAKE#

PCIE_WAKE#

INTEGRATED uC

1
0_0402_5%

G8

2
R993

C8

USB_RCOMP

INTEGRATED uC

1
<32> LAN_PCIE_WAKE#

C1272 1
2
@ 100_0402_5%

1
R1160

USBCLK/14M_25M_48M_OSC

USB OC

demo circuit
<40> SLP_S3#
<40> SLP_S5#
<40> PWRBTN_OUT#
<6,40,50> SB_PWRGD
<11> SUS_STAT#

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

HD AUDIO

R540
10K_0402_5%

E1
E2
LID use RI#
H7
F5
G1
H2
H1
SUS_STAT#
K3
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
W15
K4
K24
F1
J2
PCIE_WAKE#
H6
F2
H_THERMTRIP# J6
NBPWRGD
W14

Part 4 of 5

SB700

+3VALW

1
R388

1 NBPWRGD
0_0402_5%

2
R1052

<11> NB_PWRGD

Touch Screen (delete)

USB-9 Card Reader (delete)

USB20_P8 <33>
USB20_N8 <33>

USB-8 MiniCard(WWAN)

USB20_P7 <38>
USB20_N7 <38>

USB-7 Fingerprint

USB20_P6 <38>
USB20_N6 <38>

USB-6 Bluetooth

USB20_P5 <24>
USB20_N5 <24>

USB-5 USB Camera

USB-4 Left side

USB-3 Dock
USB20_P2 <38>
USB20_N2 <38>

USB-2 Left Side

USB20_P1 <38>
USB20_N1 <38>

USB-1 Right side

USB20_P0 <38>
USB20_N0 <38>

USB-0 Right side (S/W Debug Port)

GPIO16 <30>
GPIO17 <30>

STRAP PIN
STRAP PIN

218S7EALA11FG_BGA528_SB700

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 USB/AC97

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

27

of

Rev
0.1
52

U15B
SATA_STX_DRX_P0
SATA_STX_DRX_N0

<31> SATA_RXN0_C
<31> SATA_RXP0_C

<38>
<38>

@ C520
@ C521

SATA_TXP2
SATA_TXN2

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SATA_STX_DRX_P2
SATA_STX_DRX_N2

<38> SATA_RXN2_C
<38> SATA_RXP2_C
<31>
<31>

C518
C519

SATA_TXP3
SATA_TXN3

SATA_STX_DRX_P3
SATA_STX_DRX_N3

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

<31> SATA_RXN3_C
<31> SATA_RXP3_C

SATA_CAL=W/S=9/20(35ohm impedance), <1"

2
R342

SATA_TX0P
SATA_TX0N

AB10
AC10

SATA_RX0N
SATA_RX0P

AE10
AD10

SATA_TX1P
SATA_TX1N

AD11
AE11

SATA_RX1N
SATA_RX1P

AB12
AC12

SATA_TX2P
SATA_TX2N

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

AE14
AD14

SATA_TX4P
SATA_TX4N

AD15
AE15

SATA_RX4N
SATA_RX4P

AB16
AC16

SATA_TX5P
SATA_TX5N

AE16
AD16

SATA_RX5N
SATA_RX5P

SATA_CAL
1
1K_0402_1%
SATA_X1

V12

SATA_CAL

Y12

SATA_X1

SATA_X2

AA12

SATA_X2

R343 10K_0402_5%
1
2
+3VS
<41> SATA_LED#

+1.2V_HT

SB700

AD9
AE9

W11

SATA_LED# W/S=5/5

Part 2 of 5

ATA 66/100/133

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SPI ROM

C512
C513

SATA_TXP0
SATA_TXN0

SERIAL ATA

<31>
<31>

93mA/2vias

XTLVDD_SATA

C523
1U_0402_6.3V4Z

L55
2
1
BLM18PG121SN1D_0603
C524
1U_0402_6.3V4Z

+XTLVDD_SATA
2

+XTLVDD_SATA_SATA >20mil

6mA/2vias

HW MONITOR

+3VS

PLLVDD_SATA

W12

+PLLVDD_SATA >20mil
2

C522
1U_0402_6.3V4Z

AA11

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1
M8
M5
M7

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

AVDD

F6

AVSS

G7

SATA_ACT#/GPIO67

SATA PWR

+PLLVDD_SATA

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

L54
2
1
BLM18PG121SN1D_0603

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

CR_WAKE# <34>

SB_INT_FLASH_SEL <39>
WLOFF# <33>
BT_COMBO_EN# <33>
EC_THERM# <40>
ACIN
<40>
BT_OFF
<38>
CAM_SHDN <24>
LFB_ID0
LFB_ID1
LFB_ID2

+SB_AVDD >20mil

5mA/2vias

SATA_X1

Y4

1 C516
1

10P_0402_50V8J 2

10P_0402_50V8J 2

1 C517

25MHz_20pF_6X25000017

R341
10M_0402_5%

+SB_AVDD
1
1

2
C525
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

Change the PCB Footprint from

Y_KDS_1BX25000CK1A_2P to
Y_6X25000017_2P

+3VALW
L56
2
1
BLM18PG121SN1D_0603

Local Frame Buffer Strapping List

Copy from Becks.

C526
2.2U_0603_6.3V4Z

LFB_ID2 LFB_ID1 LFB_ID0

SATA_X2

Hynix

Qimonda

Samsung

SATA_X1/X2=W/S=4/20(55ohm impedance), <3"

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.

+3VALW

+3VALW

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1 @ R11562
10K_0402_5%
1 @ R11582
10K_0402_5%

Title

LFB_ID2

R1155 1

2 1K_0402_5%

LFB_ID1

R1157 1

2 1K_0402_5%

LFB_ID0

R1159 1

2 1K_0402_5%

Compal Electronics, Inc.

SB700 SATA/IDE/SPI

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

28

of

52

+1.2V_SB_CORE >100mil

510mA/4vias

131mA/4vias

2
2
2
2
2
2
2
2

Part 3 of 5

+3.3V_SB_IDE >50mil

1
1
1

+PCIE_VDDR >100mil

600mA/4vias
+PCIE_VDDR

@ C546
@ C545
@C548
@C551
@ C550

+1.2V_HT
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z

+1.2V_SATA >50mil

567mA/4vias
+1.2V_SATA
L63
AA14
2
1
FBMA-L11-201209-221LMA30T_0805
AB18
AA15
2
1
AA17
C566
22U_A_4VM
AC18
C567 1
AD17
2 10U_0805_10V4Z
C568 1
2 10U_0805_10V4Z
AE17
C571 1
2 0.1U_0402_16V4Z
C572 1
2 0.1U_0402_16V4Z

+3VALW

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

+S5_3V

A17
A24
B17
J4
J5
L1
L2

1
R564

1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2
2
2
2
2
2

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

C556
C559
C561
C562
C563
C564
C565

+1.2VALW
L64

G2
G4

+1.2VALW

+1.2_USB >20mil
A10
B10

L65

1U_0402_6.3V4Z
2
0.1U_0402_16V4Z 2

0_0603_5%

1
22U_A_4VM
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2

0_0603_5%
1
1

C569
C570

C573
C574
C575

1
1

+V5_VREF >20mil

1mA/2vias

+AVDD_USB

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

1
1
1
1
1
1
1

1
1
1
1
1
1

113mA/2vias
+S5_1.2V
197mA/2vias
+1.2_USB

USB_PHY_1.2V_1
USB_PHY_1.2V_2

USB I/O

C576
C577
C580
C581
C583
C582
C584

2
2
2
2
2
2

+S5_1.2V >20mil
S5_1.2V_1
S5_1.2V_2

+AVDD_USB
L66
2
1
FBMA-L11-201209-221LMA30T_0805

2
0_0805_5%
2
+

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

1
1
1
1
1
1

658mA/4vias

2
2
1
1
2

32mA/2vias

+AVDD_USB >50mil

+3VALW

1
1
2
2
1

+S5_3V >20mil

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

3.3V_S5 I/O

1
22U_A_4VM
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

A-LINK I/O

CORE S5

P18
P19
P20
P21
R22
R24
R25

+1.2V_HT

L60
2
1
0_0603_5%

+1.2V_CKVDD

L21
L22
L24
L25

2
1
FBMA-L11-201209-221LMA30T_0805
C552
C553
C555
C554
C558
C557
C560

2
2
2
2
2
2

SB700

+1.2V_HT

POWER

L61
+1.2V_HT

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

CLKGEN I/O

1
22U_A_4VM
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

IDE/FLSH I/O

Y20
AA21
AA22
AE25

@ C543
@ C544
@ C547
@ C536

1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
0_0805_5%
2
C529
C532
1
C534
1
C538
1
C537
1
C527
1
C540
1

+1.2V_CKVDD >30mil

SATA I/O

+3VS

+3.3V_SB_IDE

1
R593

138mA/2vias

71mA/3vias

0_0603_5%
1
2

@ R12

U15E

+1.2VALW

+1.2V_SB_CORE

L15
M12
M14
N13
P12
P14
R11
R15
T16

V5_VREF

AE7

+V5_VREF

AVDDCK_3.3V

J16

+AVDDCK_3.3V

AVDDCK_1.2V
AVDDC

1K_0402_5% 2

K17

C578
+AVDDCK_1.2V0.1U_0402_16V4Z

E9

+AVDDC

C579
1U_0603_10V4Z
1

D14

1 R346

+5VS

+3VS

H18
J17
J22
K25
M16
M17
M21
P16

CH751H-40PT_SOD323-2

+AVDDC=W/S=20/10mil
L67
2
1
BLM18PG121SN1D_0603

17mA/2vias

2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

F9

+3VALW

C585

C586

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

GROUND

1
1
1
1
1
1
1
1

1
22U_A_4VM
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

CORE S0

C528
C531
C530
C533
C549
C535
C539
C541
C542

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

PCI/GPIO I/O

+3VS
1

SB700

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

U15C

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
3

L17

218S7EALA11FG_BGA528_SB700

+AVDDCK_1.2V >20mil
+AVDDCK_3.3V >20mil

62mA/2vias

47mA/2vias

+AVDDCK_1.2V

+3V
+AVDD_USB

1 @ R11492
0_0805_5%

+AVDDC

1 @ R50 2
0_0603_5%

+1.2_USB

1 @ R51 2
0_0603_5%

L68
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z

+1.2V_HT

C587

C588

+1.2V

+AVDDCK_3.3V

L69
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2
0.1U_0402_16V4Z

+3VS

1 C589
1 C590

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 PWR/GND

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

29

of

Rev
0.1
52

REQUIRED STRAPS
PULL
HIGH

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5

AZ_RST_CD#

BOOTFAIL
TIMER
ENABLED

USE
DEBUG
STRAPS

RESERVED

RESERVED

ENABLE PCI
MEM BOOT

LPC_CLK1

RTC_CLK

LPC_CLK0

CLKGEN
ENABLED

INTERNAL
RTC

EC
ENABLED

GP17

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI
MEM BOOT

CLKGEN
DISABLED

DE FAULT

DE FAULT

DE FAULT

DE FAULT

Internal pull up

R355
10K_0402_5%
2
1

+3VALW

R354
10K_0402_5%
2
1

+3VALW

R353
10K_0402_5%
2
1

+3VALW

R352
10K_0402_5%
2
1

+3VALW

R351
10K_0402_5%
2
1

+3VALW

L,L = FWH ROM

R350
10K_0402_5%
2
1

+3VS

L,H = LPC ROM (Default)

DE FAULT

R349
10K_0402_5%
2
1

+3VS

EC
DISABLED

R348
10K_0402_5%
2
1

+3VS

H,L = SPI ROM

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

R347
10K_0402_5%
2
1

+3VS

GP16

H,H = Reserved

DE FAULT

PULL
LOW

+3VALW

R356
10K_0402_5%
2
1

<26>
PCICLK2
<26,39> CLK_PCI_SIO
<26>
PCI_CLK4
<26>
PCI_CLK5
<26,40> CLK_PCI_EC
<26>
LPCCLK1
<26>
RTC_CLK
<27,40> HDARST#
<27>
GPIO17
<27>
GPIO16

R366
2.2K_0402_5%
2
1

R365
2.2K_0402_5%
2
1

R364
10K_0402_5%
2
1

R363
2.2K_0402_5%
2
1

R362
10K_0402_5%
2
1

R360
10K_0402_5%
2
1

R361
10K_0402_5%
2
1

R359
10K_0402_5%
2
1

R358
10K_0402_5%
2
1

R357
10K_0402_5%
2
1

DEBUG STRAPS

PULL
LOW

PCI_AD24

PCI_AD23

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DE FAULT

DE FAULT

DE FAULT

DE FAULT

DE FAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

R378
2.2K_0402_5%
2
1

R377
2.2K_0402_5%
2
1

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R373
2.2K_0402_5%
2
1

<26>
<26>
<26>
<26>
<26>
<26>

PCI_AD25

USE ACPI
BCLK

R376
2.2K_0402_5%
2
1

PULL
HIGH

PCI_AD26

USE PCI
PLL

R375
2.2K_0402_5%
2
1

PCI_AD28

PCI_AD27

USE
LONG
RESET

R374
2.2K_0402_5%
2
1

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 STRAPS

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

30

of

52

HDD Connector
JP9

1
C594

1
C591

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C595
0.1U_0402_16V4Z

C593
10U_0805_10V4Z

+5VS

2
2
0.1U_0402_16V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

Pleace near HD CONN (JP23)

+3VS_HDD1
10U_0805_10V4Z
C1032

@R1009
1
2
0_0805_5%

1
@ C1033

2
0.1U_0402_16V4Z

1
@ C1034

C1035
0.1U_0402_16V4Z

+3VS

2
2 @
0.1U_0402_16V4Z

1
2
3
4
5
6
7

SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K

SATA_TXP0 <28>
SATA_TXN0 <28>

1 C592 SATA_RXN0_C
1 C596 SATA_RXP0_C

SATA_RXN0_C <28>
SATA_RXP0_C <28>

Near CONN side.

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS_HDD1

+5VS

CONN@ SUYIN_127072FR022G523_RV

Pleace near HD CONN (JP23)

9/20 LTCX0007Y00

Multi-Bay Connector-option(deltet)

CD-ROM Connector
+5VS
JP11

Placea caps. near ODD CONN.

1
C615

10U_0805_10V4Z

1U_0603_10V4Z

1
C614

C613

0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C616
10U_0805_10V4Z

DP
V5
V5
MD
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13

SATA_TXP3
SATA_TXN3
0.01U_0402_16V7K
SATA_RXN3
2
SATA_RXP3
2
0.01U_0402_16V7K
R970 0_0402_5%
1
2

1 C612 SATA_RXN3_C
1 C611 SATA_RXP3_C

SATA_TXP3 <28>
SATA_TXN3 <28>
SATA_RXN3_C <28>
SATA_RXP3_C <28>

Near CONN side.

+5VS

om

SUYIN_127382FR013G509ZR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

HDD/CDROM

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

9/20 DC020709041

31

of

Rev
0.1
52

+3V_LAN

<22> CLKREQ_LAN#

2 R384
1
1K_0402_5%
2 R382
1
15K_0402_5%

CLKREQB

RSET

ISOLATEB

LANWAKEB
ISOLATEB

LAN_X1
LAN_X2

41
42

CKXTAL1
CKXTAL2

LAN_X2

C653

25

RTL8102EL

C654

23
24

NC
NC

7
14
31
47

GND
GND
GND
GND

22

GNDTX

LED0

38

LAN_ACTIVE#

MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC

2
3
5
6
8
9
11
12

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

NC

0.1U_0402_16V4Z
1
C641
0.1U_0402_16V4Z

1
C640

0.1U_0402_16V4Z

1
C639

1
C638

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C637
2

C636
2

C644

1
C633

Q144
0.1U_0402_16V4Z
SI2301BDS-T1-E3_SOT23-3

2
C1271

<40> LAN_POWER_OFF

PAD-OPEN 4x4m

1
C632

0.1U_0402_16V4Z

PJP605

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VALW

for U20 VDD33 pins-1, 29, 37 and 40.

R1148
100K_0402_5%

0.1U_0402_16V4Z

10U_0805_10V4Z

VCTRL12A

48

+VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

19
30
36
13
10

+VDDTX_LAN

NC

39

NC
VCTRL12D

44
45

VDD33
VDD33

29
37

AVDD33
NC
NC

1
40
43

+1.2V_DVDD 1
C622
0.1U_0402_16V4Z

1
@ C628
C623

1
C629
0.1U_0402_16V4Z
2

R295
3.6K_0402_5%
1
2

2
2
1U_0603_10V4Z

+VCTRL12D

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

2 R298
1
0_0603_5%

+3V_LAN
@ C630

+3V_LAN

U17

+1.2V_DVDD

4
3
2
1

C631
0.1U_0402_16V4Z

2
2
10U_0805_10V4Z

DO
DI
SK
CS

GND
NC
NC
VCC

5
6
7
8

1
C340 0.1U_0402_16V4Z
+3V_LAN

AT93C46-10SU-2.7_SO8
R296 AT93C46A(3.3V)
10K_0402_5%

REFCLK_P
REFCLK_M

26
28

25MHz_20pF_6X25000017
2

HSIN

17
18

46

Y5
LAN_X1

16

PERSTB

R385 2.49K_0402_1%
RSET
1
2

+3VS

HSIP

27

<11,14,15,26,33,34,39,40> PLT_RST#

<27> LAN_PCIE_WAKE#

HSON

15

33
34
35
32

<22> CLK_PCIE_LAN
<22> CLK_PCIE_LAN#

21

+1.2V_DVDD

for U20 VDD12 pins-10, 13, 30, 36, 39.

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS

<10> PCIE_ITX_C_PRX_N3

HSOP

2
G

<10> PCIE_ITX_C_PRX_P3

20

<10> PCIE_PTX_C_IRX_N3
1

0.1U_0402_16V7K
1 PCIE_PTX_IRX_P3
0.1U_0402_16V7K
1 PCIE_PTX_IRX_N3

U20
C485
2
C488
2

<10> PCIE_PTX_C_IRX_P3

27P_0402_50V8J
2 27P_0402_50V8J
2

RTL8102EL-GR_LQFP48_7X7

LAN Conn.
JRJ45
+3V_LAN
LAN_ACTIVE#
3

C648 0.01U_0402_16V7K
1
2
C647 0.01U_0402_16V7K
1
2

LAN_MDI0LAN_MDI0+

1
2
3
4
5
6
7
8

RD+
RDCT
NC
NC
CT
TD+
TD-

LAN_ACTIVITY#

RX+
RXCT
NC
NC
CT
TX+
TX-

RJ45_MIDI1RJ45_MIDI1+
1
2
1
C661 0.01U_0603_100V7-M
C662 0.01U_0603_100V7-M
1
2
1
RJ45_MIDI0RJ45_MIDI0+

16
15
14
13
12
11
10
9

2
R394 2
R396 2

75_0402_1%

@C656
68P_0402_50V8K
RJ45_MIDI1-

C658
1
2

75_0402_1% 1000P_1206_2KV7K

LEF8423A-R

1
LAN_EECLK

Yellow LED+

14

Yellow LED-

U19
LAN_MDI1LAN_MDI1+

2 R391
1
300_0402_5%

13

@C657
68P_0402_50V8K
2 R395
1
300_0402_5%

SHLD1
PR4DETECT PIN1

PR4+

PR2-

PR3-

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

+3V_LAN

11

LAN_LINK#

12

16
3

DETCET PIN2

10

SHLD1

15

Green LED+
Green LEDFOX_JM36113-P1122-7F
CONN@

9/20 DC234001G00

9/20 DC234001G00

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RealTek_8102EL_10/100

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

32

of

52

Mini Card Slot 1---WLAN

+3VS

+3VS_WLAN

Max 1A

+1.5VS

2 R407 1
0_0805_5%
C665
0.1U_0402_16V4Z

+1.5VS_WLAN

Max 0.5A
R406 2
1
0_0805_5%

C666
4.7U_0805_10V4Z

C668

0.01U_0402_16V7K
2

C669

C670

+3VALW_WLAN
@ R1043
1
R1042
1
1
C667

4.7U_0805_10V4Z

+3VALW
+3VS_WLAN
0_0603_5%
2
0_0603_5%
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
JP14
MINI_PCIE_WAKE#
CH_DATA
CH_CLK

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
0_0603_5%
2
39
0_0603_5%
41
2
43
45
47
49
CH_CLK
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

<22> CLK_PCIE_MCARD2#
<22> CLK_PCIE_MCARD2

<10> PCIE_PTX_C_IRX_N2
<10> PCIE_PTX_C_IRX_P2
<10> PCIE_ITX_C_PRX_N2
<10> PCIE_ITX_C_PRX_P2

+3VS_WLAN

<28> BT_COMBO_EN#

@ R46 1
@ R47 1

1 R49

0_0402_5%

R48

+3VS_WLAN
+1.5VS_WLAN

PLT_RST#

WLOFF# <28>
PLT_RST# <11,14,15,26,32,34,39,40>
+3VALW_WLAN
Max 0.3A

SMB_CK_CLK1
SMB_CK_DAT1

SMB_CK_CLK1 <27>
SMB_CK_DAT1 <27>
USB20_N8 <27>
USB20_P8 <27>

WL_LED#

WL_LED# <41>

G1
G2
G3
G3

1
3
5
7
9
11
13
15

CONN@
FOX_AS0B226-S99N-7F

53
54
55
56

<27> MINI_PCIE_WAKE#
<38>
CH_DATA
<38>
CH_CLK
<22> CLKREQ_MCARD2#

4.7K_0402_5%
2

9/20 SP01000HS00/SP01000LX00
9/20 STANDOFF (H=7.5 mm) ES000000D00

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

WLAN

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

33

of

Rev
0.1
52

SDCLK

Card Reader Connector

+VCC_4IN1

MSCLK
2

+VCC_OUT

XDCE#

+VCC_4IN1
2

JREAD

0.1U_0402_16V4Z

1
5

OUT
OUT

C895

GND

G5250C2T1U_SOT23-5
@ C896

2
2

@ R123

1U_0603_10V4Z

150K_0402_5%

reserved power circuit

+VCC_4IN1

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

SDCMD_MSBS_XDWE#
XDWP#_SDWP#
XD_ALE
XD_CD#
XD_RB#
XD_RE#
XDCE#
XD_CLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

Use 0805 type and over 20 mils

trace width on both side
+VCC_OUT

+VCC_4IN1

41
42

R383 2
1
0_0805_5%

SD-VCC
MS-VCC

21
28

+VCC_4IN1

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

SD-WP-SW

XDWP#_SDWP#

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

XD-VCC

7 IN 1 CONN

2
@ C902
100P_0402_25V8K

2
@ C901
100P_0402_25V8K

R45
XDWP#_SDWP# 2

40mil

IN
EN

@ R411
100_0402_5%

@ U22
3
4

@ R412
100_0402_5%

+3VS

@ R413
100_0402_5%

XD_RB#

2
@ C900
100P_0402_25V8K

10K_0402_5%
1

2
1
R106 10K_0402_5%

Place R413,C902 close to JREAD.20; R412,C901

close to JREAD.26; R411,C900 close to JREAD.37

+3VS_CR
R121 4.7K_0402_5%
XDCD0#_SDCD#2
1
XDCD1#_MSCD# 2

R111 4.7K_0402_5%
1

D40
2

XD_CD#

1
3

7IN1 GND
7IN1 GND

1
DAN202U_SC70

CONN@ TAITW_R015-B10-LM

C689
10U_0805_10V4Z

C696
270P_0402_50V7K

9/20 ???
C694
0.1U_0402_16V4Z

place near pin 5 and

pin 10.

+1.8VS

+1.8VS_OUT
2

+3VS

20mil

1
C892

@ R124

2
2
10U_0805_10V4Z

2 2
G

10K_0402_5%

CPPE#

Power Circuit

CR_WAKE#

2
0.1U_0402_16V4Z

0_0402_5%
1
2
@ R369

+3VS_CR

+3VS

D3 Normal 30mA Deepest 3mA

U23

2N7002_SOT23-3

<28>

2
1
0.1U_0402_16V4Z C695

@ Q54
1

CR_CPPE#

<27>

@ R1020
0.1U_0402_16V4Z
1000P_0402_50V7K 2
1
1
1
1
0_0603_5%
C688
C687
C893

<22> CLK_PCIE_MCARD0#
<22> CLK_PCIE_MCARD0

XDCD0#_SDCD#

<10> PCIE_ITX_C_PRX_N1
<10> PCIE_ITX_C_PRX_P1
C693 1
C697 1

<10> PCIE_PTX_C_IRX_N1
<10> PCIE_PTX_C_IRX_P1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

2 R114
1
10K_0402_1%
+3VS_CR
+5VS_LED

APREXT
12mil

2 R409
1
10K_0402_5%

3
4

APCLKN
APCLKP

9
8

APRXN
APRXP

11
12

APTXN
APTXP

7
38
39

PCIES_EN
PCIES

T45 PAD
D5
HT-F196BP5_WHITE

19
20
44
18
37

Ripple 250mV

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

XRSTN
XTEST

13
14

SEEDAT
SEECLK

15
16

CR1_CD1N
CR1_CD0N

NC
NC
NC

34
35
36

17

CR1_PCTLN

C691

C692

Ripple 100mV
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

Ripple 250mV

+1.8VS_OUT
1

XD_SD_MS_D0
C686
XD_SD_MS_D1
0.1U_0402_16V4Z
2
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
R457 2
XDWP#_SDWP#
R456 2
XD_CLE
R455 2
XD_SD_D4
XD_SD_D5
Place
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

C690
0.1U_0402_16V4Z

1 22_0402_5%
1 22_0402_5%
1 22_0402_5%

SDCLK
MSCLK
XDCE#

R455~R457 close to U23.42

Strap pin for JMicro

+3VS_CR
2

10K_0402_5%

10K_0402_5%

200K_0402_5%

1
R405
1
R122

XD_CLE

1
R86

XD_RE#

XD_ALE

XDCD1#_MSCD#
XDCD0#_SDCD#

45mA DV33
DV33
DV33
25mA DV18
DV18

JMB385

2
2

CPPE#

Ripple 100mV

APREXT

1
2

<11,14,15,26,32,33,39,40> PLT_RST#

5
10
30

1mA

R370
200_0402_5%

APVDD
APV18
TAV33

58mA

2 R1021 1
0_0603_5%

+VCC_OUT
D

2
G

CR_LED

21

8mA sink current

Q53
2N7002_SOT23-3
S

APGND

use for PWR_EN#

GND
GND
GND
GND

CR1_LEDN

6
24
31
32
33

R1051
4.7K_0402_5%
2

JMB385-LGEZ0A_LQFP48_7X7

White LED: VF=3V, IF = 10mA, Res = 200 ohm

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

PCI-E I/F Card Reader-JM385

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

34

of

52

CODEC POWER
+3VS_HDA

+3VDD_CODEC
+3VS

R885
1
2
BLM18BD601SN1D_0603
C734

+3VS

C733

+VDDA_CODEC

R978
1
2
BLM18BD601SN1D_0603

0.1U_0402_16V4Z
1

+VDDA_CODEC_R

R979
1
2
0_0603_5%

C1046

C730

0.1U_0402_16V4Z

1U_0603_10V4Z

+5VALW

W=40Mil
1
C728

C731
1U_0603_10V4Z

+VDDA_CODEC

U32

2
0.1U_0402_16V4Z

<40,43,45,47,51> SUSP#

IN

GND

SHDN

OUT

BYP

G9191-475T1U_SOT23-5 1

0.1U_0402_16V4Z

(4.75V(4.56~4.94V))
300mA

C729
2.2U_0805_16V4Z

C732

0.1U_0402_16V4Z

U27

25

AVDD1*

38

AVDD2**

+3VS_HDA

32

@
R525
47_0402_5%

<27> HDA_SDOUT_CODEC

SDO

R522 1

SDI_CODEC

HDA_SYNC_CODEC

10

<27> HDA_RST#_CODEC

HDA_RST#_CODEC

11

RESET#

46

DMIC_CLK

2
<24>
<27>

SB_SPKR

R524 1

2 47K_0402_5%

R523 1

2 10K_0402_5% MONO_IN 1

C956
<40>

EC_BEEP

R1174 1
+VDDA_CODEC_R

22_0402_5%
2

@ R230 1

DMIC_CLK

2 0.1U_0402_16V4Z

@C979

31

GPIO 5

43

GPIO 6

44

SPDIF OUT1 / GPIO 7

45

SPDIF OUT0

48

40
SENSEB#

DMIC_DAT <24>

13

VREFOUT_B

R548
R569
R571
R570
C951

SENSE

41

HP_OUTR

PORTA_L

39

HP_OUTL

PORTB_R

22

MIC_EXTR

PORTB_L

21

MIC_EXTL

1
1
1
1

2
2
2
2

5.1K_0402_1%
20K_0402_1%
39.2K_0402_1%
10K_0402_1%
0.1U_0402_16V4Z

1
2
HP_OUTR <36>

1
C981
1
C982

2
2

1U_0603_10V6K

NC

PORTC_R

24

MIC_INR

NC

PORTC_L

23

MIC_INL

19

NC
PORTD_R

36

LINE_OUT_R

LINE_OUT_R <36>

PORTD_L

35

LINE_OUT_L

LINE_OUT_L <36>

VREFFILT

PORTE_R

15

26

AVSS1*

PORTE_L

14

42

AVSS2**
PORTF_R

17

DVSS**
PORTF_L

16

HP Jack & Dock

MIC_EXT_R <36>

1U_0603_10V6K

18

27

EXTMIC_DET# <36>
JACK_DET# <36>
INTMIC_DET# <36>

HP_OUTL <36>

37

NC

+VDDA_CODEC_R

PORTA_R

NC / OTP

VREFOUT_B <36>

SENSE_B / NC

20
10U_0805_10V4Z
VC_REFA
C744 1
2

28
29

SENSE_A

EAPD_CODEC <40>

34

VREFOUT-B
VREFOUT-C

SYNC

EAPD_CODEC

30

VREFOUT-E / GPIO 4

33
2
1
C913
1U_0603_10V4Z CAP2
MONO_INR
2
12 PCBEEP
0.1U_0402_16V4Z
C955

2 47K_0402_5%
R982 1
2 5.1K_0402_1%

0.1U_0402_16V4Z

BITCLK

<27> HDA_SYNC_CODEC

1
@C745
33P_0402_50V8K

2 33_0402_5%

VOL_DN/DMIC_1/GPIO 2

MONO_OUT

HDA_SDOUT_CODEC

<27> HDA_SDIN0

DVDD_IO

<27> HDA_BITCLK_CODEC

47

VOL_UP/DMIC_0/GPIO 1

GPIO 3

HDA_BITCLK_CODEC

HDA_BITCLK_CODEC

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

Jack MIC

1
C983

2
0.022U_0603_25V7K

@ R911
0_0603_5%

1
C984

MIC_EXT_L <36>
MIC_IN_R <36>

DVDD_CORE

R1128
0_0603_5%

Internal MIC

DVDD_CORE*

+VDDA_CODEC_R

+3VDD_CODEC

2
1
2
0.022U_0603_25V7K
@ R1127 0_0603_5%

MIC_IN_L <36>

Internal SPKR.
DOCK MIC
3

92HD71B7X5NLGXA1X8_QFN48_7X7

@ C746
1
2
0.1U_0402_16V4Z
@ C747
1
2
0.1U_0402_16V4Z

39.2K

39.2K

@ R1006
1
2
0_0402_5%

20K

20K

@R195
1
2
0_0805_5%

10K

10K

R198
1
2
0_1206_5%

5.11K

H
A

5.11K

GND

Compal Secret Data

Security Classification
GNDA

GNDA
B

Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.

om

Resistor

l.c

Port

<36>

2007/10/11

Issued Date

ai

Resistor

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Compal Electronics, Inc.

nf
@
ho
tm

@ C749
1
2
0.1U_0402_16V4Z

Port

Audio Codec-IDT9271B7
Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

@ C748
1
2
0.1U_0402_16V4Z

SENSE B

Sheet

he
x

SENSE A

35

of

Rev
0.1
52

+5VAMP

+5VS
R594
1
2
0_1206_5%

C1051

SPEAKER

GAIN0

GAIN1

6dB

10dB

Av(inv)

JP20
SPKL+
SPKLSPKR+
SPKR-

+5VS
0.1U_0402_16V4Z

10 dB

2
1

9/20 SP02000CW00

SPKR+

ROUT-

14

SPKR-

LOUT+

SPKL+

LOUT-

SPKL-

R1003
100K_0402_5%

@ D55
PSOT24C_SOT23-3

@ R1004
100K_0402_5%

@ D56
PSOT24C_SOT23-3
1

18

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

2
5

2 0.022U_0603_25V7K
2
0.022U_0402_16V7K

LIN+

LIN-

INTMIC IN

19

SHUTDOWN

20
13
11
1

NC

12

BYPASS

10

+VDDA_CODEC

R906
0_0402_5%
1

AMP_BYPASS
1

C743
1U_0603_10V4Z
1
2

R904
4.7K_0402_5%

Keep 10 mil width

+VDDA_CODEC

1
1

ROUT+

@ R905
4.7K_0402_5%

R951
100K_0402_5%
2

EC_MUTE#

GND1
GND2
GND3
GND4

<40> EC_MUTE#

2 0.022U_0603_25V7K
2
0.022U_0402_16V7K

21.6dB

GND1
GND2
E&T_3806-F04N-02R
CONN@

C1044
10U_0805_10V4Z
<35>
<35>

1
2
3
4

MIC_IN_L
MIC_IN_R

TPA6017A2_TSSOP20

2
1
R955 10K_0402_5%

+3VS

D
Q151
1

2
G

9/20 SP02000H700/SP02000H900

2N7002_SOT23-3

2
G

2N7002_SOT23-3

GND1
GND2
ACES_88231-04001
CONN@

Q160

1
2
3
4

5
6

<40> ANA_MIC_DET

<35> INTMIC_DET#

JP42

C1055

1
1

GAIN1

RIN-

C763

C1041

17

2
100P_0402_50V8J

5
6

C762

<35> LINE_OUT_L

C1054

2 0.022U_0603_25V7K
2
0.022U_0402_16V7K

GAIN0

15.6dB

C761

1
2
3
4

C1040
R1005
0_0402_5%
2
1

1
1

RIN+

R1001
100K_0402_5%

C1053

@ R1000
100K_0402_5%

THERMAL PAD

C1050

2 0.022U_0603_25V7K
2
0.022U_0402_16V7K

1
1

16
15
6
VDD
PVDD1
PVDD2

<35> LINE_OUT_R

C1052

21

C1049
R1002
0_0402_5%
2
1

C760

U28

1
2
3
4

C767

C766
10U_0805_10V4Z

0.1U_0402_16V4Z

Close to CODEC U27

Audio/B & CIR

3

JP43
R909
2
1
0_0402_5%

C742 1

R907

MIC_EXT_R

MIC_EXT_L

MIC_EXT_L

<35> EXTMIC_DET#
<35> JACK_DET#

EXTMIC_DET#
JACK_DET#

4.7K_0402_5%
2

<35>

MIC_EXT_R

1
2
3
4
5
6
7
8
9
10
11
12
13
14

HP_OUT_R
HP_OUT_L

R908

4.7K_0402_5%

<35>

MIC_EXT_R
MIC_EXT_L

1U_0603_10V4Z

<35> VREFOUT_B

<40>

CIR_ IN

CIR_IN
+5VL

EXTMIC IN

1
2
3
4
5
6
7
8
9
10
11
12
13
14

CONN@ ACES_87213-1400G

09/13 update
9/20 SP02000H800
HP_OUTR

<35>

HP_OUTL

C774 150U_Y_6.3VM
1
2
+

<35>

C773 150U_Y_6.3VM
1
2

HP_OUT_R

HP_OUT_L

HP OUT For M/B

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMP & Audio Jack

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

36

of

52

ACCELEROMETER
20mil
+3VS

20mil

+3VS_ACL
@ D44
2

@ R959
1

+3VS_ACL_IO
0_0603_5%
2

CH751H-40PT_SOD323-2
@ C1030
0.1U_0402_16V4Z

1
@ C1031

10U_0805_6.3V6M

SMB_CK_CLK0

+3VS_ACL_IO
@ R997
0_0402_5%
1
2

14

SMB_CK_CLK0 <8,9,22,27>

0011101b

Vdd_IO

GND

SDA / SDI / SDO

13

SDO

12

Reserved

Reserved

11

GND

GND

10

GND

INT 2

Vdd

INT 1

SMB_CK_DAT0

SMB_CK_DAT0 <8,9,22,27>

@ R998
0_0402_5%
1
2

PAD
ACCEL_INT

T53

ACCEL_INT <26>

+3VS_ACL

SCL / SPC

@ U63

VDDIO absolute man

rating is VDD+0.1

R1146
100K_0402_5%

LIS302DLTR_LGA14_3x5

2
@ R999

CS

1
10K_0402_5%

Must be placed in the center of the system.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Accelerometer

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

37

of

Rev
0.1
52

Left side

USB CONNECTOR

Left side
Max 2.5A
+USB_VCCA

+5VALW

TPS2061IDGN_MSOP8~N
4.7U_0805_10V4Z
2

1
+
2

1000P_0402_50V7K
C791

W=100mils

8
7
6
5

OUT
OUT
OUT
OC#

0.1U_0402_16V4Z
C790

GND
IN
IN
EN#

C789
150U_D_6.3VM

C788

1
2
3
4

USB20_N2_R

IO1

IO2 GND

USB20_P2_R
<27>
<27>

R1140
1
1
R1142

USB20_N2
USB20_P2

0_0402_5%
2 USB20_N2_R
2 USB20_P2_R
0_0402_5%

D12

SATA_TXN2

JP47
JESAT

VIN

1
2
3
4

@ PRTR5V0U2X_SOT143-4

+USB_VCCA

Right side USB 0&1 Board Conn

Max 0.5A
+USB_VCCA

ESATA5/USB2 combination Connector

D11
+USB_VCCA

U40
1

VIN

IO1

IO2 GND

SATA_TXP2

@ PRTR5V0U2X_SOT143-4

<28>
<28>

SATA_TXP2
SATA_TXN2

SATA_TXP2
SATA_TXN2
@ C792 2
@ C793 2

<28> SATA_RXN2_C
<28> SATA_RXP2_C

1 0.01U_0402_16V7KSATA_RXN2
1 0.01U_0402_16V7KSATA_RXP2

USB_EN#

1
2
3
4
5
6
7
8
9
10

+5VALW

USB

VBUS
DD+
GND

<40>
<27>
<27>

5
6
7
8
9
10
11

GND
A+
ESATA <27>
<27>
AGND
BB+
GND

12
13
14
15

GND
GND
GND
GND

USB_EN#
R1141 1
1
R1143
R1144 1
1
R1145

USB_EN#
USB20_N0
USB20_P0
USB20_N1
USB20_P1

0_0402_5%
2
2
0_0402_5%
0_0402_5%
2
2
0_0402_5%

USB20N0
USB20P0
USB20N1
USB20P1

11
12

1
2
3
4
5
6
7
8
9
10

GND1
GND2
ACES_87213-1000G

9/20 SP02000DX00
CONN@

TYCO_1759576-1

9/20 DC020709060

Finger printer

BT Connector
@ R622 0_0603_5%
1
2
@ SI2301BDS-T1-E3_SOT23-3

30mil
+3VS_FB

USB20_N7
USB20_P7

<27> USB20_N7
<27> USB20_P7
D21

USB20_N7

@ R581 0_0603_5%
1
2

IO1

IO2 GND

USB20_P7

USB20_P6 <27>
USB20_N6 <27>
BT_LED <41>
CH_DATA <33>
CH_CLK <33>

1K_0402_5%
1K_0402_5%

2
2

0612 no install
D16

ACES_88231-08001
CONN@

+3VAUX_BT
USB20_N6

9/20 SP02000HC00/SP02000HB00

VIN

IO1

IO2 GND

USB20_P6

@ PRTR5V0U2X_SOT143-4
+3VALW
Q24

ACES_85201-06051
CONN@

+3VAUX_BT 40mil
SI2301BDS-T1-E3_SOT23-3

9/20 SP01000B000
1

C798

R519

1U_0603_10V4Z

100K_0402_5%

C799

C800

C801

0.1U_0402_16V4Z

@ PRTR5V0U2X_SOT143-4

@ R517 1
@ R518 1

VIN

1
2
3
4
5
6
GND
GND

+3VAUX_BT
USB20_P6
USB20_N6

JP39
1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND1
GND2

+3VS

1
@ C832
0.1U_0402_16V4Z

G
USB_EN#

+3VS_FB

JP32

20070209 Add for FPR

Q31

+3VALW

0.01U_0402_16V7K

<28>

BT_OFF

R520
1
2
10K_0402_5%

1
C802

4.7U_0805_10V4Z

2
0.1U_0402_16V4Z

Check BT power consumption < 1A

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

USB, BT, eSATA,FPR

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

38

of

52

+3VAL
2
0_0402_5%
+3VL
2
0_0402_5% 1
C803

0.1U_0402_16V4Z

<40,44> SMB_EC_CK1
<40,44> SMB_EC_DA1

SPI Flash (8Mb*1)

1
R996
1

R521
100K_0402_5%

U31
8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2
GND

0.1U_0402_16V4Z

<40>

SPI_CS#

<40>

SPI_CLK

<40> EC_SO_SPI_SI

VCC

HOLD

INT_SPI_CS#
2
1
0_0402_5%
SPI_CLK_R
6
2
0_0402_5%
1 EC_SO_SPI_SI_R 5
0_0402_5%

1
@ R221
1
R227
2
R229

CONN@
U29

1
2
3
4

AT24C16AN-10SI-2.7_SO8

20mils

C484

+3VL
1
@ R995
+3VALW

R526
100K_0402_5%

&U29
VSS

45@ SST25VF080B-50-4C-S2AF_SO8
9/20 SA000012E00/SA00000XT00

S
C
D

EC_SI_SPI_SO_R

2
R223

1
0_0402_5%

EC_SI_SPI_SO <40>

WIESON G6179 8P SPI

9/20 SP07000F500
+3VALW
C624
2
JP50

<28> SB_INT_FLASH_SEL

1
3
5
7

0.1U_0402_16V4Z
2
4
6
8

2
4
6
8

+3VALW

INT_FLASH_EN#
SPI_CLK_R
EC_SO_SPI_SI_R

U24

R1175

@ E&T_2941-G08N-00E~D
2

INT_SPI_CS#

22_0402_5%

C:Chg. PN to LTC00000200

R313

1
3
5
7

G Vcc

SPI_CS#
EC_SI_SPI_SO_R

INT_FLASH_EN#

100K_0402_5%
2

SPI_CS#

NC7SZ32P5X_NL_SC70-5

LPC Debug Port

LPC Debug Port

+3VS
JP41

<26,40> SIRQ
<26,40> LPC_AD3
<26,40> LPC_AD1

LPC_DRQ#

SIRQ

PLT_RST#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LPC_FRAME#

10

CLK_PCI_SIO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

LPC_DRQ# <26>
PLT_RST# <11,14,15,26,32,33,34,40>
LPC_AD2 <26,40>
LPC_AD0 <26,40>
CLK_PCI_SIO <26,30>

<26,40> LPC_FRAME#

@ DEBUG_PAD

9/20 ??????

@ R232
22_0402_5%

CLK_14M_SIO

R137 1

CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#
PLT_RST#
2 @ 0_0402_5%
CLK_PCI_SIO2
SIRQ

CLK_14M_SIO <22>

+3VALW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

@ R310
100_0402_5%
2

H31

CLK_PCI_SIO2 <26>

@ C502
100P_0402_25V8K

@ ACES_85201-2005
1

CLK_PCI_SIO2

9/20 DC233105000
@ C486
22P_0402_50V8J

@ R1172
22_0402_5%
1

@ C1275
22P_0402_50V8J

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

BIOS ROM/Debug Tool

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

39

of

Rev
0.1
52

Keyboard Connector

2
2
0.1U_0402_16V4Z

C808

+3VL

C809

2
2
1000P_0402_50V7K

+3VL_EC
R527
1

+EC_AVCC

2
0_0805_5%

VCC
VCC
VCC
VCC
VCC
VCC

U33

<11,14,15,26,32,33,34,39> PLT_RST#
2
47K_0402_5%
<27>
EC_SCI#
<27,30> HDARST#

R533 1

C811

+5VALW

R531
R532

4.7K_0402_5%
2
1 SMB_EC_DA1
4.7K_0402_5%
2
1 SMB_EC_CK1
4.7K_0402_5%
2
1 SMB_EC_DA2
4.7K_0402_5%
2
1 SMB_EC_CK2
<39,44>
<39,44>
<6,21>
<6,21>

+3VALW

<27>
<27>
<27>
<41>

R565
10K_0402_5%

+3VL_EC

R538
10K_0402_5%

2
1

R543
4.7K_0402_5%

LID_SW#

CONA#

<41>

+3VS

ON/OFF#

<43>

77
78
79
80

WL_BLUE_BTN
CONA#

VLDT_EN

E51_TXD
R1176
2 0_0402_5%
1 E51_RXD
ON/OFF#

<43> DIM_LED
<41> NUM_LED#
C813
15P_0402_50V8J
1
2

C RY2

Y7
3

NC

OUT

NC

IN

122
123

68
70
71
72

73
74
89
90
91
92
93
95
121
127

CIR_ IN

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

GPI

XCLK1
XCLK0

@
R545
20M_0402_5%

32.768KHZ_12.5PF_1TJS125DJ4A420P
1

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
DA Output
IREF/DA2/GPIO3E
KSI0/GPIO30
DA3/GPIO3F
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

R1154
10K_0402_5%

WL_BLUE_BTN

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

<32> LAN_POWER_OFF

DOCK_SLP_BTN#

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

<41> WL_BLUE_BTN
<6,27> H_THERMTRIP#

+3VL_EC

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

R529

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

1
0.1U_0402_16V4Z

R528

12
13
37
20
38

BATT_TEMP
BATT_OVP

GND
GND
GND
GND
GND

+3VL_EC

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

63
64
65
66
75
76

C RY1

1
L80
0_0603_5%

1
C816

TP_BTN#

TP_CLK
TP_DATA

@ R537
4.7K_0402_5%
2
1
DOCK_VOL_UP#
DOCK_VOL_DWN#

KB Back Light Conn

+5VS_LED
JP48

<41>
<41>

5
6

FSTCHG
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON

SB_PWRGD
BKOFF#

EC_RSMRST# <27>
EC_LID_OUT# <27>
EC_ON
<43,46>
WL_BLUE_LED# <41>
SB_PWRGD <6,27,50>
BKOFF# <24>

TP_LED#

TP_LED#

1
2
3
4

SUSP#
PWRBTN_OUT#

2
C814

9/20 SP01000KC00/SP010009O10
+3VS

DOCK_VOL_UP#

+5VL

R589
10K_0402_5%
2
1

DOCK_VOL_DWN# 2

1
R590
10K_0402_5%

<36>

FSTCHG <45>
STD_ADP <45>
CAPS_LED# <41>
BAT_LED# <41>
ON/OFFBTN_LED# <41>
SYSON
<41,43,48>

G1
G2

1
2
3
4

ACES_85201-04051
CONN@

<50>

EC_SI_SPI_SO <39>
EC_SO_SPI_SI <39>
SPI_CLK <39>
SPI_CS# <39>
2
1
R1153 10K_0402_5%
CIR_IN

9/20 SP01000FF00/SP01000G300

select SPI ROM or LPC ROM

VGATE
2
100K_0402_5%

119
120
126
128

100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K

GND1
GND2

EC_MUTE# <36>
USB_EN# <38>
1
2
R558 10K_0402_5%

I2C_INT
MUTE_LED
TP_CLK
TP_DATA

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

ACES_85201-24051
CONN@

DAC_BRIG <24>
VCTRL
<45>
IREF
<45>
AC_SET
<45>

IR EF

R1044

25
26

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
1
R541 10K_0402_5%
VR_ON
2
1
AC_IN
D54
CH751H-40PT_SOD323-2
2
1
+3VALW
R1040
100K_0402_5%
1
2
C1073
100P_0402_50V8J

<41>

<50>
<45,46>

R534
10K_0402_5%
1
2
R535
10K_0402_5%
TP_DATA
1
2

+5V_TP

TP_CLK

ACIN

<28>

SUSP#

SYSON

R536
100K_0402_5%

ENBKL
<16>
EAPD_CODEC <35>
EC_THERM# <28>
SUSP#
<35,43,45,47,51>
PWRBTN_OUT# <27>
PCI_SERR# <26>

R539
100K_0402_5%

4.7U_0805_10V4Z

Need 1uf for 926 C version

+3VS

KB926QFC0_LQFP128_14X14
TP_BTN#

R1050
1
2
10K_0402_5%

SA00001J540(C0) S IC KB926QFC0 LQFP 128P

+EC_AVCC

97
98
99
109

BATT_TEMP <44>
BATT_OVP <44>
ADP_I
<45>
ADP_ID
<44>
TP_BTN# <41>
ANA_MIC_DET <36>

@ C213
@ C609
@ C754
@ C756
@ C757
@ C758
@ C759
@ C764
@ C768
@ C769
@ C822
@ C823
@ C824
@ C825
@ C826
@ C875
@ C876
@ C877
@ C878
@ C884
@ C885
@ C886
@ C887
@ C888

SA00001J530(B1) S IC KB926QFB1 LQFP 128P KBC

+3VL_EC

C815
15P_0402_50V8J

83
84
85
86
87
88

INV_PWM <24>
FAN_PWM <4>
EC_BEEP <35>
ACOFF
<45>
0.01U_0402_16V7K
C812
ECAGND
1
2

ACOFF

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

<26,30> CLK_PCI_EC

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

PWM Output

AGND

2
@ 33_0402_5%

INV_PWM
FAN_PWM

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

69

21
23
26
27

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ECAGND

R530
2

GATEA20
1
KB_RST#
2
SIRQ
3
LPC_LFRAME# 4
LPC_AD3
5
LPC_AD2
7
LPC_AD1
8
LPC_AD0
10

11
24
35
94
113

C810
1

@ 15P_0402_50V8J

<27>
GATEA20
<27>
KB_RST#
<26,39> SIRQ
<26,39> LPC_FRAME#
<26,39> LPC_AD3
<26,39> LPC_AD2
<26,39> LPC_AD1
<26,39> LPC_AD0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C807

1000P_0402_50V7K

67

C806

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

AVCC

C805

0.1U_0402_16V4Z
1

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

+3VS

For EMI

JP33

+3VL_EC

2
0.1U_0402_16V4Z

L81
1

2
0_0603_5%

EC DEBUG port
@
JP34
1
2
3
4

1
2
3
4

E51_RXD
E51_TXD

+5VALW

Compal Secret Data

Security Classification
2007/10/11

Issued Date

ACES_85205-0400

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

9/20 SP020007200

Title

Compal Electronics, Inc.

EC KB926/KB conn

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

40

of

52

for debug only

ON/OFF Button Connector(delete)TP ON/OFF

M/B TO TP/B
+3VALW

TP_DATA
TP_CLK
3

Max 0.5A
+5V_TP
1

ON/OFF#
3

6
5

SW3

TP_BTN#

@ D31
PSOT24C_SOT23-3

JP37

<40>
5
6

5
6

SMT1-05_4P

TP_BTN#

@ C819
0.1U_0402_16V4Z

0_0603_5%
2

R1038
@10K_0402_5%

SW1
SMT1-05-A_4P

@ R1178
1

TOP
BTN

1
2
3
4

G1
G2

1
2
3
4

TP_CLK
TP_DATA

ACES_85201-04051
CONN@

9/20
SP01000KC00/SP01E000900

MDC 1.5 Conn.

9/20 SP01000J100
9/20 STANDOFF (H= 5.0 mm) ES000000800

+5VALW

+5V_TP
R235
0_0603_5%
1
2
@ Q85
SI2301BDS-T1-E3_SOT23-3

<40>
<40>

@ C820
100P_0402_50V8J 2

Max 0.5A

TP_CLK
TP_DATA

@ C821
2 100P_0402_50V8J

CONN@ JP25
D

1 R495
2HDA_SDIN1_MDC
33_0402_5%

+3VS
R645

+3VS

SWITCH BOARD.

2
4
6
8
10
12

@ 10K_0402_5%
HDA_BITCLK_MDC <27>

<27> HDA_SYNC_MDC
<27> HDA_SDIN1
<27> HDA_RST#_MDC

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

<27> HDA_SDOUT_MDC

1
3
5
7
9
11

C780
@4.7U_0805_10V4Z

Q34
3

2
G

<40,43,48> SYSON

1
C779
2

@ R496
10_0402_5%

ACES_88018-124G

13
14
15
16
17
18

1
C778
2

+5VALW_LED
1

GND
GND
GND
GND
GND
GND

+3VS

+5VS_LED

@ 2N7002_SOT23-3

JP36

Connector for MDC Rev1.5

1000P_0402_50V7K
0.1U_0402_16V4Z

ON/OFFBTN_LED#

<40> ON/OFFBTN_LED#
@ C777
10P_0402_50V8J

WL_BLUE_LED#

<40>
<40>

HDD LED

1
2
3
4
5
6
7
8
9
10
11
12

<40> WL_BLUE_BTN

NUM_LED#
ON/OFF#

ON/OFF#

TouchPAD ON/OFF LED

1
2
3
4
5
6
7
8
9
10
GND
GND

ACES_85201-1005N
CONN@

+5VS_LED

+5VS

9/20 SP01000H400

HT-297UY5/BP5_YELLOW-WHITE
On (TP_LED#=L)-> Amber
Off (TP_LED#=H)-> White

+3VALW

<40>

2
G
Q153
2N7002_SOT23-3

Battery Charge LED

TP_LED#

LID_SW#

JP40
1
2
3

1
2 GND
3 GND

4
5
3

ACES_88231-03041
CONN@

TP_LED# <40>

9/20 SP020020710

WLAN and BT LED inform pin to KBC

+5VALW_LED

WHITE

+3VS

D50
1

<40> BAT_LED#

+5VS

1 R550
2
200_0402_5%

CAPS LOCK LED

+5VS_LED

WHITE

WL_BLUE_LED#

<40> WL_BLUE_LED#

D30
<40> CAPS_LED#

R1152
1
2
10K_0402_5%

R989
1
2
10K_0402_5%

HT-F196BP5_WHITE
SC500004W00

Q172B
2N7002DW-7-F_SOT363-6

4 2

D45 SC500004C00

10K_0402_5%

Reed switch BOARD.

AMBER
YELLOW

R985

2
6
<28>

1 R988
2
200_0402_5%

1 R552
2
200_0402_5%

6
1
Q158A
2N7002DW-7-F_SOT363-6

Q158B
2N7002DW-7-F_SOT363-6

HT-F196BP5_WHITE
SC500004W00

BT_LED

<38>

+5VALW_LED

WHITE

POWER LED

WL_LED# <33>

R1025
100K_0402_5%

D27
2

1 R549
2
200_0402_5%

om

ON/OFFBTN_LED#

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

TP,MDC,ON/OFF,S/W,LED,Reed
Size Document Number
Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

HT-F196BP5_WHITE
SC500004W00

White LED: VF=3V, IF = 10mA, Res = 200 ohm

Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

Sheet

he
x

2
SATA_LED#
Q172A
2N7002DW-7-F_SOT363-6

HT-F196BP5_WHITE
SC500004W00

WHITE
WHITE

D46

10K_0402_5%

R1177

+5VS

WHITE

R984
390_0402_5%
2 2

R983
200_0402_5%
+5VS_LED

41

of

Rev
0.1
52

H47, H48 -Stand off of MODEM on BOT Side

H45
@ H_4P2

1
1

H41
@ H_2P8

H46
@ H_4P2

H48
@ H_4P0

H47
@ H_4P0

H44
@ H_4P2

H43
@ H_4P2

H42
@ H_2P8

H40
@ H_2P8

H37
@ H_2P8

H36
@ H_2P8

H35
@ H_2P8

H34
@ H_2P8

H33
@ H_2P8

H53
H54
H55
@ H_3P3X0P6N @ H_3P3X0P6N @ H_5P6N

H56
@ H_5P0X2P5N

CF1
1

CF2
1

CF3
1

CF4

Compal Secret Data

Security Classification
2007/10/11

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SCREW HOLE

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

42

of

52

DIM LED

+5VALW_LED
Q32
3

+5VALW

+5VS

R587
10K_0402_5%

4.7U_0805_10V4Z

D
C834

Q17
SUSP
2
2N7002_SOT23-3
G
S

1
2
3
4

S
S
S
G

1
C1024 4.7U_0805_10V4Z

C1026

1U_0402_6.3V4Z
SI4800BDY_SO8 RUNON_S4
2 R956
1
330K_0402_5%
1
D
C1025
Q138

B+

<40>

DIM_LED

DIM_LED

C840
2

B+

C1023

D
D
D
D

Q51
2N7002_SOT23-3

2
G

+5VS_LED

SYSON#
2
G
2N7002_SOT23-3

RUNON

1U_0402_6.3V4Z
RUNON
2 R152
1
330K_0402_5%

Q137
8
7
6
5

1
4.7U_0805_10V4Z

C838

C836
0.1U_0402_16V4Z

+5VS

4.7U_0805_10V4Z

1
2
3
4

SI4800BDY_SO8

SI4800BDY_SO8
C864

S
S
S
G

1U_0402_6.3V4Z

C839

D
D
D
D

0.01U_0402_25V7K

8
7
6
5

4.7U_0805_10V4Z

S
S
S
G

Q14

D
D
D
D

C835

C833
1
2
3
4

0.01U_0402_25V7K

Q35
8
7
6
5

4.7U_0805_10V4Z

+3V

1
1

+3VALW

+3VS

+3VALW TO +3V

+3VALW

+5VALW

+3VALW TO +3VS

+5VALW TO +5VS

SI2301BDS-T1-E3_SOT23-3

Q166
SI2301BDS-T1-E3_SOT23-3

C1069
0.1U_0402_16V4Z

1
C1029

RUNON_S4

2
+1.2V

+3V

Q141
2N7002_SOT23-3

Q42

09/13 update (Del +V_DDR_MCH_REFP)

SI@ 2N7002_SOT23-3

SYSON#

SUSP

100K_0402_5%
SUSP

Q52

2
G

<40,41,48> SYSON

S 2N7002_SOT23-3

Q39
2
G
2N7002_SOT23-3

SUSP#

<18,49>
<13>

VLDT_EN#

<35,40,45,47,51><40>

VLDT_EN

VLDT_EN#
D

VLDT_EN 2
G

Q40
2N7002_SOT23-3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DC/DC Circuits

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/10/11

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

S 2N7002_SOT23-3

SUSP

Q38
SYSON 2
G
2N7002_SOT23-3

Q50

2
G

SYSON#

S 2N7002_SOT23-3

SUSP

Q49

<49>

R597

100K_0402_5%

R294
470_0805_5%

1
1

1
1

R596

100K_0402_5%

R293
470_0805_5%

S 2N7002_SOT23-3

SYSON# 2
G
3

R292
470_0805_5%

D
Q47

2
G

R595
R288
470_0805_5%

+1.1VS

+5VL

+1.5VS

Change to +3VL(same as EC)

to avoid leakage

+5VL

2
G

EC_ON#

Q41

+0.9V

Q44
2N7002_SOT23-3

2
1
S 2N7002_SOT23-3

SYSON# 2
G

SI@ 470_0805_5%

1
Q37

S 2N7002_SOT23-3

VLDT_EN#2
G

2
G

+3VS

SUSP

EC_ON#

<40,46> EC_ON

+5VL

R368

Q48

S 2N7002_SOT23-3

2
G

SUSP

1
Q46

1
3

S 2N7002_SOT23-3

+1.2VALW

R284
470_0805_5%

R280
470_0805_5%

R279
470_0805_5%

R239
470_0805_5%

2
G

+1.8V
2

+1.2V_HT
2

+1.8VS

+5VS

SUSP

100K_0402_5%

Reserve until SI-1 stage after SB

USB PHY power saving report

Discharge circuit

R598

SYSON# 2
G
3

SYSON# 2
G

R958
470_0805_5%
2

R957
470_0805_5%
Q140
2N7002_SOT23-3

+5VL
1

Q12
VLDT_EN#
2
G
2N7002_SOT23-3

4.7U_0805_10V4Z

SUSP
2
G
Q13
2N7002_SOT23-3

C837

D
C849
2
0.01U_0402_25V7K

B+

C1028

1U_0402_6.3V4Z
Q139

B+

C1027
1
2
3

R138 2
1
330K_0402_5%

8
7
6
5

1U_0402_6.3V4Z
2 R233
1
330K_0402_5%

IRF8113PBF_SO8

4.7U_0805_10V4Z

1.8VS_ENABLE

C847

C862

4.7U_0805_10V4Z

C842

1U_0402_6.3V4Z

1
2
3

C846

8
7
6
5

+1.2V

C841
10U_0805_10V4Z

+1.2VALW

C848

4.7U_0805_10V4Z

1
2
3

+1.2V_HT

Q11
IRF8113PBF_SO8

8
7
6
5

+1.2VALW

0.01U_0402_25V7K

Q4
IRF8113PBF_SO8

+1.2VALW TO +1.2V

+1.2VALW TO +1.2V_HT

+1.8VS

4.7U_0805_10V4Z

+1.8V TO +1.8VS
+1.8V

43

of

Rev
0.1
52

BATT1

45@ CR2032 RTC BATTERY

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2

BATT

PJP2
8
7
6
5
4
3
2
1
9
10

EC_SMD
EC_SMC

PD2
@SM05_SOT23

105K_0402_1%
PR6 1
2

PU1A
LM358ADT_SO8

PR5
10K_0402_5%
2
1

P
0

BATT_OVP <40>

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

PL3
HCB2012KF-121T50_0805
1
2

1
2
PL4
HCB2012KF-121T50_0805

BATT

1
2

PC8
1000P_0402_50V7K

PC9
0.01U_0402_50V4Z

8
7
6
5
4
3
2
1
GND
GND

VMB

PC5
1000P_0402_50V7K
2
1

PC4
100P_0402_50V8J
2
1

@PJSOT24C_SOT23-3

PC3
1000P_0402_50V7K

PD1
2

2
1
PC2
100P_0402_50V8J

PJP1

ADPIN

3
PL1
SMB3025500YA_2P
1
2

5
4
3
2
1

VIN

RLZ3.6B_LL34

1
2
PR3
10K_0402_5%
0.01U_0402_25V7K
PC6

5
4
3
2
1

2
ADP_SIGNAL

@1000P_0402_50V7K

+5VALW

PD4
PR2
10K_0402_5%

ACES_88334-057N

PC12
1

PR8
100_0402_5%

2 1

ADP_ID <40>

0.01U_0402_25V7K
PC1
2
1

AC_LED <45>

SUYIN_200275MR008GXOLZR

PR7
47K_0402_1%
1
2

+5VS

PD3
@SM24.TC_SOT23-3

1
3

PQ1
SSM3K7002FU_SC70-3

2
G

PU1B
LM358ADT_SO8

PC11
1000P_0402_50V7K

ENTRIP2 <6,46>

BATT_TEMP <40>

PR15
150K_0402_1%
2

2
PR17
1K_0402_5%

PR12
2.55K_0402_1%

PC10
0.22U_0603_10V7K

2
PR11
150K_0402_1%

+5VALW

+3VLP

PR16
6.49K_0402_1%
1
2

<45>
1

BAT_ID

ENTRIP1 <46>

PR10
15K_0402_1%
1
2

SMB_EC_CK1 <39,40>

SMB_EC_CK1

10KB_0603_1%_TH11-3H103FT

SMB_EC_DA1 <39,40>
2

PH1
SMB_EC_DA1

PR14
100_0402_5%

PR13
100_0402_5%

CPU

PQ2
SSM3K7002FU_SC70-3

2
G

Compal Secret Data

Security Classification
2007/08/02

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DC Connector/CPU_OTP

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

44

of

52

P4

B+

BATT
VIN

P2
PQ102
AM4835EP-T1-PF_SO8

VDAC

PH

25

12

VADJ

REGN

24

RE GN 2

LODRV

23

DL _CHG

EXTPWR

1
2

DPMDET

3
2
1

1U_0603_10V6K

21

1
1

20

19

18

BAT_ID

<44>

PC122
@0.1U_0603_25V7K

<40>

IREF

PR121
200K_0402_1%

PR122
681K_0402_1%
1
2

PC124
0.1U_0603_25V7K

BATT

PR120
2
1
133K_0402_1%

17

16

IADAPT

PR123
1M_0402_5%
1
2

47K_0402_5%
PR119
2
G

PC123
0.1U_0402_10V7K

BQ24740VREF

D
PQ111
SSM3K7002FU_SC70-3

PC118
0.1U_0402_10V7K

CELLS

SRP

SRN

BAT

IADAPT

PC119

PC120
0.22U_0603_10V7K
2
1

ADP_I

BATT

PR112
0.015_1206_1%
1
2

5
6
7
8
PQ110
AO4466_SO8

22

PR117
100K_0402_5%
1
2

PC121
100P_0402_50V8J
2
1

PR118
10K_0402_5%
1
2

Charge Detector
<40>

15

PR116
39K_0402_5%

PGND
SRSET

ISYNSET

14

PQ106
DTC115EUA_SC70-3

4
PR115
100K_0402_1%

5
6
7
8

PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2

13

1
2

PC105
4.7U_0805_25V6-K

1
2

PD102
VA DJ

P2
BQ24740VREF

PR124
1K_0402_5%
1
2

VIN

VIN

PACIN
1

8
P
G

2
1

LM393DG_SO8

PR134
10K_0402_5%

PD103
RLZ4.3B_LL34

S
FSTCHG#
1
2
G

FSTCHG

STD_ADP <40>

PR136
49.9K_0402_1%
1
2

P2

PQ113
SSM3K7002FU_SC70-3
3

<40>

1.24VREF

PR133
10K_0603_0.1%

PU102B

PU102A
LM393DG_SO8

PQ112
SSM3K7002FU_SC70-3

2
G

PC126
0.047U_0402_16V7K

<40,46>

PR127
10K_0402_1%

PR135
10K_0603_0.1%

PR132
100K_0402_5%
2
1

1
-

PR130
2.15K_0402_1%
1
2

PR128
10K_0402_5%
2
1

1
2

CH GEN#

PC125
0.1U_0603_25V7K

PR129
10K_0402_1%
2
1

1
PR131
133K_0402_1%

PR126
100K_0402_1%

+3VLP

AC_IN

+3VLP
PR125
47_1206_5%

VIN

<40>

PQ108
AO4466_SO8

3
2
1
11

ACOFF

PC116
4.7U_0805_25V6-K

DH_CHG
LX_CHG

PC115
4.7U_0805_25V6-K
2
1

26

PU101
BQ24740RHDR_QFN28_5X5

VREF

S PQ114
SSM3K7002FU_SC70-3

HIDRV

10

PC111
0.1U_0402_10V7K
1
2
4

BST_CHG

2
G

27

PR139
100K_0402_5%
1
2

PC114
4.7U_0805_25V6-K

28

BTST

RLS4148_LL34-2

PC117
1U_0603_10V6K

+3VLP

PC113
4.7U_0805_25V6-K
2
1

PVCC

AGND

VCTRL

PC104
4.7U_0805_25V6-K

1
2
2
1

CHGEN

ACP

ACN

4
LPMD

ACDET

7
LPREF
IADSLP

<40>

<44> AC_LED

PA CIN

PC110
1U_0805_25V6K
1
2

VIN

PR105
10K_0402_5%

CHG_B+

29

PR103
47K_0402_5%
1
2

A COFF#

PR108
10_1206_5%
1
2
TP

8
7
6
5

CHG_B+

+3VLP

PD101
RLS4148_LL34-2

PR114
@0_0402_5%
1
2

PC103
4.7U_0805_25V6-K

1
2

PC108

PC109
@0.1U_0603_25V7K

BQ24740VREF

PR113
143K_0402_1%

PC102
1U_0603_6.3V6M
1
2

PQ109
SSM3K7002FU_SC70-3
3

ACSET

PR110
0_0402_5%
1
2

1U_0603_6.3V6M

2
G

1
2
3

PL101
HCB2012KF-121T50_0805
2

2
1

PR111
3K_0402_1%
1
2

A COFF#

CH GEN#

PC112
1
2

PA CIN

0.1U_0603_25V7K

PC107
@0.01U_0402_16V7K

PR109
<35,40,43,47,51> SUSP#
150K_0402_5%
PQ107
SSM3K7002FU_SC70-3

ACSET
1

PC106
0.22U_0603_16V7K
2
1

AC_SET

2
1
PR106
200K_0402_5%

1
2

2
G

ACDET

PR104
0_0402_5%
1
2

DTA144EUA_SC70-3
PQ104

PQ105
DTC115EUA_SC70-3

PR102
0.012_2512_1%
1
2

8
7
6
5

<40>

1
2
3

PR101
47K_0402_5%
1
2

PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2

PQ103
AM4835EP-T1-PF_SO8

1
2
3

8
7
6
5

PQ101
AM4835EP-T1-PF_SO8

S
PU103
4

CATHODE

NC

NC

1.24VREF

ANODE

l.c

APL1431LBBC-TR_SOT23-5

Compal Secret Data

2007/05/29

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Charger

Size

Document Number

LA-4112P
Date:

Wednesday, November 21, 2007

D

Rev
0.1

ai

Issued Date

he
x

Security Classification

nf
@
ho
tm

ai

22P_0402_50V8J

100K_0402_1%
PR138

PC127
PR137
20K_0402_1%

REF

om

ACDET

Sheet

45

of

52

2VREF_51125

PR304
20K_0402_1%
2

20

LX_5V

12

DRVL2

DRVL1

19

LG_5V

18

EN0

5
6
7
8

1
2

PC313
4.7U_0805_25V6-K

PL303
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2

+3VLP
PU301
TPS51125RGER_QFN24_4X4

+5VALWP

1
+

4
PQ304
FDS6690AS_NL_SO8

PC310
220U_6.3VM_R15

2
3
2
1

PR317
100K_0402_5%

1
2
3

14

3
2
1

LL1

VCLK

LL2

13

PC305
4.7U_0805_25V6-K
2
1

1
ENTRIP1

VFB1

VREF

21

11

VREG5

DRVH1

4
PQ303
AO4466_SO8

TONSEL

VBST1

DRVH2

+
2

VBST2

1
PC309
220U_6.3VM_R15

22

PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2

VIN

LG_3V

23

10

17

UG_3V

PGOOD

PQ302
AO4466_SO8
4

5
6
7
8

VREG3

24
UG1_5V

16

8
7
6
5

1
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

BST_3V

GND

1
2
3

UG1_3V

+3VALWP

PR307
PR309
0_0402_5%
1
2

VO1

VO2

15

VFB2

P PAD

SKIPSEL

PQ301
AO4466_SO8

PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1

ENTRIP2

25
2

PC306
10U_0805_6.3V6M

PR306
133K_0402_1%
2

B++

8
7
6
5

1
2

PC303
4.7U_0805_25V6-K

PR305
137K_0402_1%
1

ENTRIP1

PR303
20K_0402_1%
1
2

+3VLP

2
PC301
2200P_0402_50V7K
2
1

PR302
30.9K_0402_1%
2

PL301
HCB2012KF-121T50_0805

B++

B+

ENTRIP2

PR301
13.7K_0402_1%
1

PC304
2200P_0402_50V7K
2
1

PC302
0.22U_0603_10V7K

VL
2

PR311
620K_0402_5%

3/5V_OK <48>
PC311
10U_0805_10V6K

B++
ENTRIP1

<6,44>

ENTRIP2

<44>

PC312
0.1U_0603_25V7K

2
G

D
PQ305
SSM3K7002FU_SC70-3

2VREF_51125

PQ306
SSM3K7002FU_SC70-3

2
G

PJP301

VL

PQ307
SSM3K7002FU_SC70-3
2
G

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m
PJP303
1

+3VALWP

+5VL

VL
PJP304

PAD-OPEN 4x4m

EC_ON <40,43>

1
PAD-OPEN 2x2m

+5VALWP

PR314
100K_0402_5%
2

PC318
0.022U_0603_25V7K

<40,45> AC_IN

PQ308
SSM3K7002FU_SC70-3
1
2
2
PR318
G
330K_0402_1%

PR313
100K_0402_5%
2

+3VL

+3VLP
PJP302

Compal Secret Data

Security Classification
2007/08/02

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

3.3VALWP/5VALWP

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

46

of

52

PR401
0_0402_5%
1
2

PL401

VFB

DH_1.1V

LL

12

LX_1.1V

TRIP

11

V5DRV

10

PR410
1
2
0_0402_5%

1
+5VALW

2
PR406
12.1K_0402_1%

1
2
PC413
@10P_0402_50V8J

PQ401
AO4466_SO8

1
2

4.7U_0805_25V6-K
PC404
2
1

PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

+1.1VSP

TPS51117RGYR_QFN14_3.5x3.5
DL_1.1V

3
2
1

PR408
1
2
11.5K_0402_1%

DH_1.1V_1

PC415
4.7U_0805_10V6K

DRVL

3
2
1

13

PGOOD

PGND

PC408
220U_D2_4VY_R25M

V5FILT

PC406
@680P_0402_50V7K

5
6
7
8

DRVH

VOUT

VBST

PC402
0.1U_0402_10V7K

B+

14

15
TP

TON

HCB1608KF-121T30_0603
1
2

PQ402
FDS6690AS_NL_SO8

VCCP_POK
1

PR411
+1.1VSP 10_0402_5%
1
2

2
PC409
1U_0603_10V6K

2
1
0_0402_5%

EN_PSV

PU401
PR404
255K_0402_1%
1
2

PR405

+1.1VS

BST1_1.1V 1

PR402
0_0402_5%

PR403
316_0402_1%

PR407
0_0402_5%
1
2

BST_1.1V
1

GND

5
6
7
8

1+5VALW

+5VALW

+1.1VSP

4.7U_0805_25V6-K
PC403
2
1

1.1V_B+

PC401
@1000P_0402_50V7K

2200P_0402_50V7K
PC405

35,40,43,45,51> SUSP#

PR409
24K_0402_1%

PC407
@0.022U_0402_16V7K

PJP401

+1.1VSP

+1.1VS

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

1.1VSP

Size

Document Number

LA-4112P
Date:

Wednesday, November 21, 2007

D

Rev
0.1

ai

Deciphered Date

he
x

2007/05/29

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

Sheet

47

of

52

+1.8VP

PR502
10.2K_0603_0.1%

PR503
18.7K_0402_1%

PR504
11.5K_0402_1%

UG_1.8V

10

LX_1.8V

11

LL2

LG_1.8V

12

DR VL2

5
6
7
8

VO1

VFB1

3
GND

PGOOD1

24

EN1

23

VBST2

VBST1

22

BST_1.2V

DR VH2

DR VH1

21

UG_1.2V

LL1

20

LX_1.2V

DR VL1

19

LG_1.2V

4
PR507
0_0402_5%
2
1

2
UG1_1.2V

1
PR509
0_0402_5%

PR512
33K_0402_5%
2

<40,41,43> SYSON

+5VALW

1
2

PC514
1U_0603_10V6K

PR514
3.3_0402_5%
PC513
@0.1U_0402_10V7K

PC512
0.1U_0402_16V7K

PR513
0_0402_5%
2

PC515
4.7U_0805_10V6K

(4A,160mils ,Via NO.=8)

(8A,320mils ,Via NO.=16)

PJP501
+1.8VP

3/5V_OK <46>

3
2
1

PR510
16.5K_0402_1%

+1.2VALWP

PC510
4.7U_0805_6.3V6K
1
2

PGND1

TRIP1

18

4
PQ504
AO4466_SO8

1
PR511
11K_0402_1%
1
2

+1.2VALWP

PL503
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2

TPS51124RGER_QFN24_4x4

17

V5FILT

V5IN
16

15

TRIP2
14

PGND2
PQ503
FDS6690AS_NL_SO8

PC507
0.1U_0402_10V7K

5
6
7
8

PC505
2200P_0402_50V7K
2
1

BST_1.8V

PQ502
AO4466_SO8

PC511
220U_D2_4VY_R25M

1
PR508

PC504
4.7U_0805_25V6-K
2
1

EN2

1
2
3

PGOOD2

13

B+

1
2
0_0402_5%

8
7
6
5
1

PC509
4.7U_0805_6.3V6K
2
1

PC508
330U_2V_M_R15M

+1.8VP

UG1_1.8V

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
2
1

B+++

3
2
1

1
2
3

+1.8VP

P PAD

4
PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1

VO2

25

PQ501
AO4466_SO8

+1.2VALWP

PL502
HCB2012KF-121T50_0805
2
1

TONSEL

PU501

8
7
6
5

+1.8VP

VFB2

1
2

PR505
0_0402_5%

PC502
2200P_0402_50V7K
2
1

1
2

PC501
4.7U_0805_25V6-K

PC517
4.7U_0805_25V6-K

B+++

PR501
14.3K_0603_0.1%

B+++

PJP502
2

+1.8V

+1.2VALWP

PAD-OPEN 4x4m

+1.2VALW

PAD-OPEN 4x4m

PJP503
4

+1.8VP

+1.8V

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/08/02

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

1.8VP/1.2VALWP

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

48

of

52

+1.8V
+1.8V

PU603

+5VALW

NC

TP

PC603
1U_0603_16V6K

G2992F1U_SO8

NC

VREF

NC

VOUT

NC

TP

+5VALW

PR606
1K_0402_1%

VOUT

VCNTL

GND

PC613
10U_0805_10V4Z

VIN

2
1

NC

VREF

5
1

NC

VCNTL

PC609
@10U_0805_10V4Z

GND

VIN

1
PR601
1K_0402_1%
2

1
2

PC601
10U_0805_10V4Z

PC602
@10U_0805_10V4Z

PU601

PC612
1U_0603_16V6K

G2992F1U_SO8

PR608
0_0402_5%

PC606
@0.1U_0402_16V7K

2
G

+1.5VSP

1
2

PR607
5.1K_0402_1%
2

<18,43> SUSP

1
PC605
10U_0805_6.3V6M

PQ602
SSM3K7002FU_SC70-3

2
G

+0.9VP

PR604
@0_0402_5%

PR603
1K_0402_1%

D
2

<18,43> SUSP

2
1
PC604
0.1U_0402_16V7K

PQ601
SSM3K7002FU_SC70-3
2

2
PR602
0_0402_5%

2
1
PC611
0.1U_0402_16V7K

VREF1.5V

<43> SYSON#

PC614
10U_0805_6.3V6M

PC610
@0.1U_0402_16V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

PAD-OPEN 3x3m

PJP603
+1.5VSP

+1.5VS

(1A,40mils ,Via NO.= 2)

+2.5VS

(500mA,40mils ,Via NO.= 1)

IN

OUT

+2.5VSP

GND
1

(2A,80mils ,Via NO.= 4)

PR605
@150_1206_5%
2

+0.9V

PC607
1U_0603_6.3V6M

+0.9VP

+3VS

PC608
4.7U_0805_6.3V6K

PJP601

PAD-OPEN 3x3m

PJP602
+2.5VSP

2
PAD-OPEN 3x3m

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

0.9VSP/2.5VSP/1.5VSP

Size Document Number

Custom
LA-4112P
Date:

Wednesday, November 21, 2007

E

ai

200810/11

Deciphered Date

Sheet

he
x

2007/08/02

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

om

49

of

Rev
0.1
52

8
7
6
5

CPU_B+

1
2
3

2
1

PC204
4.7U_0805_25V6-K
1

UGATE NB1

PHASE NB

LGATE NB

1
PR209
0_0402_5%

PR204
22K_0402_1%
1
2

PR203
0_0402_5%

PR206
0_0402_5%
2
1

1
2
3

PC202
220U_B2_2.5VM

1
2
<6> VDD_NB_FB_L

PQ202
AO4466_SO8

PQ201
AO4466_SO8
8
7
6
5

10U_0805_6.3V6M
PC201

<6> VDD_NB_FB_H

2
1
4.7UH_SIQB74B-4R7PF_4A_20%

PC203
2200P_0402_50V7K

PL201

+CPU_CORE_NB

PC205
1000P_0402_50V7K

PR205
2_0402_5%
1
2

<6> CPU_VDD1_FB_H

1
PR241
0_0402_5%

1
PR239
0_0402_5%

<6> CPU_VDD1_FB_L

PC242
2 1000P_0402_50V7K

1
2

PC214
2200P_0402_50V7K
2
1

PC213
4.7U_0805_25V6-K
2
1

PC212
4.7U_0805_25V6-K
2
1

D
D
D
D
G
S
S
S

PR221
14K_0402_1%
2
1

PC218
@680P_0603_50V8J

1
1 2

PR220
@4.7_1206_5%

ISP 0

PR229
@4.7_1206_5%
1 2

ISP 1

AO4456_SO8

3
2
1

PQ208
3
2
1

PQ207

+CPU_CORE_1

PR236
6.81K_0402_1%
2

PC222
2200P_0402_50V7K
2
1

PC221
4.7U_0805_25V6-K
2
1
1

ISP 1

1
PR238
54.9K_0402_1%
2
1
PJP201

PC232
1200P_0402_50V7K
PR240
1K_0402_1%
2
1

1
+CPU_CORE_1
PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%

PR233
6.65K_0603_1%
1
2

PC229
0.1U_0603_25V7K

AO4456_SO8

PC231
180P_0402_50V8J
1

PC220
4.7U_0805_25V6-K
2
1

PC226
@680P_0603_50V8J

PC230
1000P_0402_50V7K
2
1

PC236
4.7U_0805_25V6-K
2
1

PC237
4.7U_0805_25V6-K
2
1

5
6
7
8
D
D
D
D

PC224
0.22U_0603_10V7K

PR231
14K_0402_1%
2
1

TP

PC219
0.1U_0603_25V7K

UGATE1_1

49

ISP1

ISN1
24

23

VW1
22

21

18
VSEN1

20

17

1
PR228
2.2_0603_5%

PR226
1
2
0_0603_5%
2
1
2

2
2

5
6
7
8
G
S
S
S

25

BOOT1

4
3
2
1

UGATE1

5
6
7
8

PHASE1

26

COMP1

27

FB1

PHASE1

3
2
1

LGATE1

UGATE1

2
<6> CPU_VDD0_FB_L

1
PR237
0_0402_5%

PQ205
AO4456_SO8

PR217
6.65K_0603_1%
1
2

CPU_B+
PQ206
SI4684DY-T1-E3_SO8

COMP0

PC241
2 1000P_0402_50V7K

+CPU_CORE_0

PL203

LGATE0

FB0

BOOT1

3
2
1

BOOT0

PHASE_NB

UGATE_NB

5
6
7
8
30

PQ204
AO4456_SO8

5
6
7
8

31

PVCC

11

PC235
4.7U_0805_25V6-K
2
1

5
6
7
8
4
3
2
1

BOOT_NB
LGATE0

10

VW0

PC234
4.7U_0805_25V6-K
2
1

1
2

2
UGATE NB

PHASE NB
38

37

39

LGATE NB
PGND_NB

LGATE_NB

OCSET_NB

RTN_NB

VSEN_NB

ISL6265IRZ-T_QFN48_6X6

PC215
1000P_0402_50V7K

1
BOOT_NB1 2
1

PR207
11.3K_0402_1%

1
43

45

44
FSET_NB

28

6.81K_0402_1%

1
PR235
0_0402_5%

COMP_NB

29

PGND1

PR232
1

46

LGATE1

VDIFF0

1
2
PC228
1000P_0402_50V7K

<6> CPU_VDD0_FB_H

VCC

OCSET

12

54.9K_0402_1%

FB_NB

PC225
1
2

1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J

47

VIN
RBIAS

16

ISP0

PR230

32

1K_0402_1%

PGND0

ENABLE

RTN1

SVC

RTN0

VDIFF1

4700P_0402_25V7K
PR227

33

15

255_0402_1%

PHASE0

PHASE0

VSEN0

95.3K_0402_1%

PC223
1
2

UGATE0

UGATE0

VSEN1

21K_0402_1%

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1

1
2
0_0603_5%
PR219

36

SVD

19

UGATE0_1

2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2

35

PWROK

RTN1

PC210
2.2U_0603_6.3V6K

PQ203
SI4684DY-T1-E3_SO8

BOOT0

VSEN0

PR224

+5VS

BOOT_NB

34

14

PR225

SVC

PR223

PL202
SMB3025500YA_2P

13

VR_ON

PGOOD

ISP 0

<40>

OFS/VFIXEN

+CPU_CORE_0

<6> CPU_SVC

SVD

ISN0

PR218
1
2
0_0402_5%
PR2221
2
0_0402_5%

CPU_SVD

PU201

B+

CPU_B+

1
@1000P_0402_50V7K
PC244
2
1
@1000P_0402_50V7K
PC245
2
1
@1000P_0402_50V7K
PC246
1
@1000P_0402_50V7K
PC247

VGATE

<6,27,40> SB_PWRGD
<6>

PR215
@10K_0402_5%

48

PR216
10K_0402_1%
2
1
<40>

40

2
PR212
0_0402_5%
1
2
PR213
@0_0402_5%
1
2

VSEN_NB

RTN0

+5VS

+3VS

PC206
0.1U_0603_16V7K

PR211
1_0603_5%

41

PC216
0.1U_0603_25V7K

PC243
1000P_0402_50V7K

CPU_B+

RTN_NB

PR208
2_0402_5%
1
2

42

33P_0402_50V8K
PC209
2
1

PC207
0.1U_0402_16V7K

2
1
2
1
PR210
PC208
44.2K_0402_1% 1200P_0402_50V7K

+5VS

+CPU_CORE_0

+CPU_CORE_1

PAD-OPEN 4x4m
PJP202

PR243
255_0402_1%
2
1

+CPU_CORE_0

+CPU_CORE_1

PAD-OPEN 4x4m

4700P_0402_25V7K
PC233

Compal Secret Data

Security Classification
2007/08/02

Issued Date

200810/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Compal Electronics, Inc.

CPU_CORE

Size Document Number

Custom
LA-4112P
Date:

Rev
0.1

Wednesday, November 21, 2007

E

Sheet

50

of

52

PR701
0_0402_5%
1
2

<35,40,43,45,47> SUSP#

PL701

PGOOD

DH_VGA

12

LX_VGA

TRIP

11

V5DRV

10

+5VALW

2 DH_VGA_1
PR707
0_0402_5%

2
PR706
12.1K_0402_1%

1
2

1
+

DL_VGA

3
2
1

PQ702
FDS6690AS_NL_SO8

PR712
36.5K_0402_1% +5VALW

PR713
@100_0402_5%
PR711
47.5K_0402_1%

+VGA_COREP

PC707
4.7U_0805_10V6K

TPS51117RGYR_QFN14_3.5x3.5

PR716
PQ703
100K_0402_5%
SSM3K7002FU_SC70-3
2
G
PQ704
D
SSM3K7002FU_SC70-3
2
1
2
G
PR715
S
200K_0402_1%

VGA_PWRSEL <16>

2
+VGA_CORE

+VGA_COREP 2

PR714
100_0402_5%

PL702
1UH_PCMC063T-1R0MN_11A_20%
1
2

DRVL

@1000P_0402_50V7K

13

LL

3
2
1

14

15
7

2
PC713

330U_D2_2.5VY_R9M

VFB

PC705
@680P_0402_50V7K

PC708

DRVH

V5FILT

VBST

PR708
10K_0402_1%

TP

VOUT

PGND

TON

+VGA_COREP1

B+

5
6
7
8

PR703
2
1
0_0402_5%

GND

PR705
255K_0402_1%
1
2

EN_PSV

PU701

PC706
0.1U_0402_10V7K

2
5
6
7
8

1+5VALW
PR702
316_0402_1%

PQ701
AO4466_SO8

PC710
2200P_0402_50V7K

PR704
0_0402_5%

PC702
1U_0603_10V6K

2 1

PC704
4.7U_0805_25V6-K

BST_VGA 1

PC703
4.7U_0805_25V6-K

VGA_B+

+5VALW

+VGA_COREP

HCB1608KF-121T30_0603
1
2

PC701
@1000P_0402_50V7K

PC714
0.01U_0402_16V7K

PJP701
+VGA_COREP

+VGA_CORE

(7A,280mils ,Via NO.= 14)

High: VGA_CORE 0.9V

Low: VGA_CORE 1.1V

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

VGA_CORE

Size

Document Number

LA-4112P
Date:

Wednesday, November 21, 2007

D

Rev
0.1

ai

2007/05/29

nf
@
ho
tm

Compal Secret Data

Security Classification
Issued Date

ai

l.c

2
PAD-OPEN 4x4m

he
x

om

PAD-OPEN 4x4m
PJP702

Sheet

51

of

52

LA-4112 Product Improvement Record (P.I.R.)

1.
D

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/10/11

Issued Date

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR
Size
Date:

Document Number
Wednesday, November 21, 2007

Rev
0.1
Sheet
1

52

of

52