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A Novel Low Power SRAM/SOI Cell Design

A novel 4 transistor (4T) self-body-biased (SBB) SRAM/SOI cell design is proposed that saves area and simplifies the manufacturing process by using a parasitic resistor under the gate of the NMOS transistor instead of a PMOS transistor. Simulations show the design can operate safely with a 0.5V supply voltage, has normal transient responses, and uses 10 times less power than a conventional 6T CMOS SRAM cell.

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ersharvan
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54 views1 page

A Novel Low Power SRAM/SOI Cell Design

A novel 4 transistor (4T) self-body-biased (SBB) SRAM/SOI cell design is proposed that saves area and simplifies the manufacturing process by using a parasitic resistor under the gate of the NMOS transistor instead of a PMOS transistor. Simulations show the design can operate safely with a 0.5V supply voltage, has normal transient responses, and uses 10 times less power than a conventional 6T CMOS SRAM cell.

Uploaded by

ersharvan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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A Novel Low Power SRAM/SOI Cell Design

Abstract
A four transistor (4T) Self-Body-Bias (SBB) structured SRAM/SOI cell is proposed. The structure
improvements and its parameters specifications are based on its performance simulations on TSUPREM4 and
MEDICI. The structure saves area and simplifies its process by using the parasitic resistor beneath the gate of
NMOS to supersede PMOS of conventional 6T CMOS SRAM. Furthermore, this structure can safely operates
with 0.5 V supply voltage, which may be prevalent in nearby future. Finally, compare to conventional 6T
CMOS
SRAM, this structures transient responses are normal and it has 10 times lower power dissipation.
Keywords: 4T SRAM, Self Body Bias, Low power

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