Scribd Logo
Upload

Welcome to Scribd!

  • 107 views

    VHDL For SR Flip-Flop

    Uploaded by

    syazo93
    This document contains VHDL code for implementing various types of flip-flops - SR flip-flop, JK flip-flop, D flip-flop, and T flip-flop. For each flip-flop type, it defines the entity with inputs and outputs, and provides the architecture with a process to specify the state transitions based on the input signals and clock.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    VHDL For SR Flip-Flop

    Uploaded by

    syazo93
    107 views4 pages
    This document contains VHDL code for implementing various types of flip-flops - SR flip-flop, JK flip-flop, D flip-flop, and T flip-flop. For each flip-flop type, it defines the entity with inputs and outputs, and provides the architecture with a process to specify the state transitions based on the input signals and clock.

    Original Description:

    DIGITAL LOGIC DESIGN

    Original Title

    VHDL

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document contains VHDL code for implementing various types of flip-flops - SR flip-flop, JK flip-flop, D flip-flop, and T flip-flop. For each flip-flop type, it defines the entity with inputs and outputs, and provides the architecture with a process to specify the state transitions based on the input signals and clock.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    107 views4 pages

    VHDL For SR Flip-Flop

    Uploaded by

    syazo93
    This document contains VHDL code for implementing various types of flip-flops - SR flip-flop, JK flip-flop, D flip-flop, and T flip-flop. For each flip-flop type, it defines the entity with inputs and outputs, and provides the architecture with a process to specify the state transitions based on the input signals and clock.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity SRff is
    Port ( S : in std_logic;
    R : in std_logic;
    Q : inout std_logic;
    QN : inout std_logic);
    end SRff;
    architecture Behavior of SRff is
    begin
    process (S,R,Q,QN)
    begin
    Q <= R NOR QN;
    QN <= S NOR Q;
    end process;
    end Behavior;
    VHDL for SR Flip-flop
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use
    IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity JKff1 is
    Port ( J : in std_logic;
    K : in std_logic;
    CLK : in std_logic;
    Q : inout std_logic;
    QN : inout std_logic);
    end JKff1;
    architecture Behaviorof JKff1 is
    begin

    process(CLK,J,K)
    begin
    if (CLK='1' and CLK'event)
    then
    if(J='0' and K='0') then
    Q <=Q;
    QN <=QN;
    elsif(J='0' and K='1') then
    Q <= '1';
    QN <= '0';
    elsif(J='1' and K='0') then
    Q <= '0';
    QN <= '1';
    elsif(J='1' and K='1') then
    Q <= NOT Q;
    QN <= NOT QN;
    end if;
    end if;
    end process;
    end Behavior;
    VHDL for JK Flip flop
    LIBRARY ieee ;
    USE ieee.std_logic_1164.all ;

    ENTITY Dff IS
    PORT ( D, Clk : IN STD_LOGIC ;
    Q : OUT STD_LOGIC) ;
    END Dff ;

    ARCHITECTURE Behavior OF Dff IS
    BEGIN
    PROCESS ( Clk )
    BEGIN
    IF Clk EVENT AND Clk = '1' THEN
    Q <= D ;
    END IF ;
    END PROCESS ;
    END Behavior ;
    VHDL for D Flip-flop
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

    ENTITY Tff is
    Port ( T : in std_logic;
    CLOCK : in std_logic;
    Q : inout std_logic;
    QN : out std_logic);
    END Tff;
    ARCHITECTURE Behavior OF Tff IS
    BEGIN
    PROCESS(CLOCK)
    BEGIN
    IF (CLOCK = '0' and CLOCK'event) THEN
    Q <= (T AND (NOT Q)) OR ((NOT T) AND Q);
    END IF;
    QN <= NOT Q;
    END PROCESS;
    END Behavior:

    VHDL for T Flip flop

    You might also like