Sheet

1 of 8

PLL Theory Tutorial
J P Silver

E-mail: [email protected]

1 ABSTRACT
This tutorials discusses the key areas of Phase
Locked Loop (PLL) design, covering the main com-
ponents of the loop ie the phase detector, divider,
VCO & loop filter.
2 INTRODUCTION [ 1,2 &3]
A phase locked loop schematic is shown in Figure 1.
Pi(s) represents the phase of the reference oscillator,
while Pe(S) is the error phase signal which is filtered
and used to drive a VCO. The transfer function of this
section is represented by G(S).

A Voltage Controlled Oscillator (VCO) can be swept
over the frequency range of interest by a control voltage.
Some of the VCO output is fed back and compared with
a reference frequency in a Phase Detector (PD). The
reference is usually a crystal oscillator but might be the
output of another loop for example. The PD generates an
error voltage, which steers the VCO to lock it to the
same frequency as the reference.

This simple system produces an output on the same fre-
quency as the reference crystal oscillator. In a practical
system it is necessary to add a programmable divider, a
reference divider and a loop filter.


Kd
MHz/V
Prescalar/
Divider
N
H(s)
Loop Filter-
Integrator
G(s)
Reference
MHz
Phase Detector
K0
V/Rad
Output
Pi(s) Pe(s)

Figure 1 Schematic of a phase locked loop
H(s) represents the feedback transfer function which in
this case is formed by the divider with division ratio =
H(s) = N.

The forward transfer function G
T
(s) is the Loop filter
transfer function G(s) * K0 * Kd.

Overall transfer function =
H(s) ). ( G 1
) ( G
T
T
s
s
+


3 LOOP COMPONENTS
3.1 PHASE DETECTOR
Phase detectors can be either analogue eg mixer or digi-
tal eg D-type flip-flop. When a mixer is used the output
consists of the sum and difference frequencies. The sum
of the frequencies are filtered out by the loop filter and
the remaining difference frequency (otherwise known as
the beatnote) when both input frequencies are the same
is the phase difference. This beatnote or phase error sig-
nal is filtered in the loop filter to produce a DC control
voltage for the VCO.

Most PLL circuits now use digital phase detectors as
shown in Figure 2.

D type
Flip-Flop
D
Clk
Q1
D type
Flip-Flop
D
Clk
Q2
Vhigh
Vhigh
F2
F1
Clear
NAND
R
C
Current
Source
Current
Sink

Figure 2 D-Type Flip-Flop Phase Detector
Refering to Figure 3. Signal F1 arrives at the D-type
flip-flop 1 first causing the output Q1 to go high (This
will stay high until F1 is clocked high again).

F2 arrives at D-type flip-flop 2 causing Q2 to go high, at
this point there will be two ones on the NAND gate
causing the output (the clear to the flip-flops) to go low
and this will cause both flip-flops to reset with Q1 & Q2
going low again. Now Q2 only went high when F2 was


Sheet
2 of 8

high but was immediately reset due to the NAND hence
we will see a pulse out of Q2. The spacing between
these pulses or the duty cycle will give the time delay
between F1 & F2. The clear is the inversion of Q2.

If we now add a capacitor to the output the pulsed volt-
age will be smoothed to give an average voltage
which, is highest when the frequencies F1 & F2 are 180
degrees apart.

F1 Input
F2 Input
Q1
Q2
Clear


Figure 3 Phase detector Input & output signals. F1
leads F2
In the case where F2 leads F1 the Q1 & Q2 outputs are
reversed as shown in Figure 4.


F1 Input
F2 Input
Q1
Q2
Clear


Figure 4 Phase Detector Outputs F2 leads F1
The third case is where the two inputs signals are in
phase resulting in a low average voltage ~ 0V from
Q1/Q2 as shown in Figure 5.

F1 Input
F2 Input
Q1
Q2
Clear


Figure 5 Both F1 & F2 in phase

The phase response of the phase detector is shown in
Figure 6, where the slope of the graph is the phase de-
tector sensitivity in V/rad.


Vhigh
Vhigh/2
0 2
Phase detector
Sensitivity
(V/rad)
= slope of graph
Typically if Vhigh = 5V then Kd = 5/2 = 0.8V/rad
Input phase difference (rad)
Output
Voltage
(V)

Figure 6 D-type flip-flop phase detector output
characteristic.
The outputs Q1 & Q2 turn on the current sources, which
either sink or source current. This will cause a voltage to
ramp up or down (as the capacitor charges up and down,
depending on the phase difference between F1 & F2)

This circuit is known as the charge pump and is
shown in Figure 8.








Sheet
3 of 8

3.2 SQUARER
The signals from the VCO and reference may well be
analogue (ie a sine wave) and if an analogue mixer is
being used as a phase detector, then these signals will
mixed to produce a DC control voltage on the IF port of
the mixer.
However if we are going to use a digital phase detector
(as described in section 3.1) we need to ensure that the
reference and RF signals are square waves. If the loop
consists of a prescaler on the RF path then the output of
the prescaler to the phase detector will be a square wave.
But if the VCO RF and/or analogue reference signal is
feed to the phase detector directly then a squarer cir-
cuit is required. A simple squarer circuit is shown in
Figure 7.

Vcc
To loop filter
0V
Re
Q1
Rb
Rfeedback
Rc
Analogue
Input
Squarewave
Output
Logic
Inverter

Figure 7 Squarer circuit. Ths common-emitter cir-
cuit uses series feedback to make the circuit broad-
band. The output logic inverter futher cleans up the
squared signal from the bipolar amplifier.

3.3 CHARGE PUMP
The charge pump consists of a push-pull current source,
current sink arrangement that connects to a shunt capaci-
tor (part of the loop filter) that effectively smooths the
clock pulses to give a constant DC level dependant on
the duty cycle of the phase detector pulsed output.

This arrangement is used to allow the designer to set the
value of the phase detector gain Kd. If using an op-amp
loop filter the outputs of the phase detector can be con-
nected together using two resistors as shown in Figure
8.

If using a charge pump (and a VCO whose control volt-
age is the within the range offered by the charge pump)
then a simple loop filter can be used, consists of the RC
circuit, as shown in Figure 8.


D type
Flip-Flop
D
Clk
Q1
D type
Flip-Flop
D
Clk
Q2
Vhigh
Vhigh
F2
F1
Clear
NAND
Rfilter
Cfilter
R
R

Figure 8 Output connection of Phase Detector if not
using a charge pump.


Vcc
To loop filter
0V
R
(mA/rad)
2
1000 *
R
Vcc
Kd

=
(V/rad)
2
Vcc
Kd

=
Q1
Q2

Figure 9 Typical Charge Pump Arrangement, with equa-
tions for calculating Kd.

3.4 SIMPLE LOOP FILTER
The simplest loop filter consists of a passive RC filter as
shown in Figure 10.

Using such a circuit is fine for VCOs that use the same
voltage supplies as the charge pump. If the control volt-
age of the VCO exceeds that generated by the charge
pump then an active op-amp based loop filter is re-
quired.


Sheet
4 of 8

frequency off - cut loop fn
change Frequency fstep
Factor Damping
time. settling Desired ts
ts. time in required frequency
final the to releative frequency Settling f Where
f * * 2
f
f
Ln -
(s) ts time Settling
frequency Detector Phase
frequency VCO Maximum

a
n
step
a
=
=
=
=
=

=
=

N


C1
C2
R1
C3
R2
From charge
pump
To VCO

Figure 10 Basic passive loop filter (Type I)

Calculation of C2

2
fn) * (2 * N
Kvco * Icp
C2

=


Calculation of R1

C2 * Kvco * Icp
N
* * 2 R1=


Calculation of C1

10
C2
C1=


Optional spurious breakthrough filter

C3 * fspur * 2
1
C3
fn * 10 fspur Let

=
=



Icp = Charge pump current (mA/rad)

Loop bandwidth

Hz
4
1

2
fn * 2

+ =



These equations allow us to calculate the loop filter re-
quirements, knowing the required lock time ts, Damping
Factor , Division ratio N, Kvco (MHz/V) and Kd
(charge pump current mA/rad).

3.5 ACTIVE LOOP FILTER
In situations where the control range of the VCO is cov-
ered by the output of the PLL a passive loop filter is
ideal. However, in most systems the VCO may have a
larger control range and in these situation active loop-
filters using an op-amp are used.

In particular a popular circuit is the differential type II
op-amp loop filter as shown Figure 11. This effectively
uses the Q1 & Q2 outputs of the phase detector directly
(bypassing the charge pump) and has the added advan-
tage of better noise reduction than a single-input op-amp
loop filter.
+
-
V1
Vin1
R1/2 R1/2
C2
R2
Vo
C1
V2
Vin2
R1/2 R1/2
C1
C2
R2
0V

Figure 11 Type II Active Differential loop filter
The differential loop filter can be simplified for analysis
as shown in Figure 12. The loop filter components can
be found from the following formulae:


Sheet
5 of 8

+
-
V1
Vin
R1/2 R1/2
C2
R2
Vo
C1

Figure 12 Simplified Type II active loop filter

0
R2
V1

sC1
1
V1

R1
V1 - Vin
=



sC2
1
R3
Vo

R2
V1
R2
R1
sC1.R1 1 V1 Vin
R1 by x
R2
1
sC1
R1
1
V1
R1
Vin

+
=

+ + =

+ + =

+ +
+
=
+
=
+
=

R2
R1
sC1.R1 1
sC2.R2
1
2
R3
Vo
- Vin
sC2.R2
1
2
R3
Vo
-
R2 by bottom & top Divide
sC2
1
R3
Vo.R2
V1
R
R

+ +
+
=
+ +
+
=
+ +
+
=
+ +
+
=
1
R1
R2
sC2 1 C2.R2.C1.R s
1 sC2.R3
Vin
Vo
sC2 1 C2.R2.C1.R s
R1
sC2.R2
1 sC2.R3
R2
sC2.R2
.R1 sC2.R2.sC1
R1
sC2.R2
sC2.R2
sC2.R2
R2
R3
sC2.R2.
sC2.R2 by bottom & top x
R2
1
sC1.R1
R1
1
sC2.R2
1
R2
R3
Vin
Vo
2
2


( ) 2sT1 sT1
sT2 1
G(s)
Vin
Vo
T2 CxR3 ; T1 CxRx ; Rx R2 R1 ; Cx C2 C1 Let
2
+
+
= =
= = = = = =


The open-loop gain can now be found with reference to
the block diagram shown in Figure 13.


ATTENUATION
1/N
Ko.Kd
V/dB
LOOP
FILTER

G(s)

Figure 13 Block diagram of the PLL Closed-loop

( )
1
2
1
2
2sT sT
) sT (1
N
Kd.Ko
LG(s)
.G(s)
N
Kd.Ko
LG(s)
Gain Loop - Open
+
+
=
=



Sheet
6 of 8

( )
) sT .G(s)(1
N
Kd.Ko
2sT sT
1
1
H(s)
.G(s)
N
Kd.Ko
1
1
1

.G(s)
N
Kd.Ko
1
.G(s)
N
Kd.Ko
H(s)
Gain Loop - Closed
2
1
2
1
+
+
+
=
+
=
+
=

3.5.1 Loop Filter Calculation of R1

.N.C2
.K K
R1
C2 for value a Assume
R1 get to Rearrange
N.R1.Cc
.K K
N.
.K K
R1.C2
(mA/rad) y sensitivit detector Phase K
(MHz/V); y sensitivit VCO Kv
. 2 bandwidth Loop

frequency detector Phase
frequency VCO
N
2
n
v
v
n
1
v
n
1
n

=
=
=
=
=
=
=
=


3.5.2 Loop filter Calculation of R2
The value of R2 is determined by setting the phase mar-
gin of the loop and is related to the damping factor .
The phase margin, being the difference between the ar-
gument of the loop gain and -180 at the frequency
where the loop gain is unity is given by:-

+ + =

= 1 4 2 2 tan

2
tan
4 2 1 -
n
1 -



For a range of damping factors we can calculate the pre-
dicted phase margin as shown in Table 1.


Damp-
i
Factor
Phase Margin
(degrees)
0 0
0.5 51.8
0.707 65.5
1 76.3

Table 1 Resulting phase margins from a given
damping factor.

If assume a damping factor of 0.707 to give us a phase
margin of 65 degrees the value of R2 is given by:

2
.R2.C2

R2.C2
2
.

n
2
2 n
=
=
=

3.5.3 Loop filter calculation of C1

R1
4.
C1
4
R1.C1


2
1

F * 10 Fc that Assume
c
c
c
n
= =
=
=
Fc

3.6 DIVIDER/PRESCALER
In most designs the VCO (Voltage controlled oscillator)
runs at a much higher frequency than the maximum fre-
quency limit of the phase detector, which is limited by
the speed of the logic employed. In these situations a
small amount of VCO output power is coupled off to a
prescaler. The prescaler is a high frequency divider but
is fed by an analogue signal but outputs a divided square
wave suitable for the phase detector circuits. Most pre-
scalers consist of a differential amplifier connected to


Sheet
7 of 8

cascaded J-K flip-flop circuits and are usually built into
the PLL chip.



The addition of the prescaler in the PLL will increase
the noise contribution in the loop by:

Noise floor of prescaler + 20*Log N

Where N is the division ratio

For example:

Prescaler device: Agilent HMMC 3128
Division ratio: 200
Phase noise @ 10KHz offset: -143dBc/Hz

Additional phase noise = 20 log 200 = 46dB

Therefore, the prescaler phase noise contribution to the
loop would be:

-143 + 46 = -97dBc/Hz @ 10KHz

3.7 VOLTAGE CONTROLLED OSCILLATOR
(VCO) [4]
The VCO is the heart of the PLL and dominates the
overall phase noise performance of the loop. As has
been shown in other tutorials the phase noise perform-
ance of the VCO (free running) is dependant on several
key design parameters including loaded Q factor, noise
figure and output power of the VCO. To determine the
approximate phase noise performance of the VCO these
parameters can be used with Leesons equation to esti-
mate the phase noise of the VCO. To verify hand calcu-
lations the key VCO parameters can be fed into the ADS
simulation shown in Figure 14.

In the ADS simulation a VCO has the following:

VCO center frequency: 2GHz,
Noise Figure: 5dB
Loaded Q: 15
Flicker Corner frequency: 30MHz

This simulates the
open-loop phase noise of
the VCO
PhaseNoiseMod
MOD2
QL=15
NF=5 dB
Fcorner=30 MHz
Rout=50 Ohm
Fnom=fcentre
Noise
Mod
Phase
VAR
VAR3
fcentre=2000MHz
Eqn
Var
HarmonicBalance
HB1
NoiseNode[1]="PNoise_OL"
NoiseOutputPort=2
NLNoiseStop=40 MHz
NLNoiseStart=100 Hz
Order[1]=7
Freq[1]=fcentre
HARMONIC BALANCE
MeasEqn
meas1
PNoise_OLout=real(PNoise_OL[0])
VCO_OLout=VCO_OL[2]
Eqn
Meas
PM_DemodTuned
DEMOD2
Sensitivity=180/pi
Fnom=fcentre
Rout=50 Ohm
P_1Tone
PORT1
Freq=fcentre
P=dbmtow(10)
Z=50 Ohm
Num=1

Figure 14 ADS simulation used to predict phase
noise performance given the resonator loaded Q,
NF, Flicker corner frequency, centre frequency and
output power.
EqnPhaseNoise=10*log(0.5*VCO_phasenoise..PNoise_OL.noise**2)
m2
indep(m2)=1.000E4
plot_vs(PhaseNoise, noisefreq)=-75.383
1E3 1E4 1E5 1E2 1E6
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-180
0
noisefreq, Hz
PhaseNoise
m2
Phase noise prediction (Bipolar device) assumimg loaded Q of 15 @2000MHz

Figure 15 Resulting simulation from Figure 14,
showing the resulting phase noise prediction with a
marker set to 10KHz frequency offset and VCO
loaded Q to 15.




Sheet
8 of 8

4 SUMMARY
This tutorial described the basic operation of a Phase
Locked loop (PLL).

A description of each component within the loop (ie
VCO, Squarer, Prescaler, Loop filter & phase detector)
was given and where necessary the relevant design
equations. Emphasis was given to the design of passive
and mire commonly active loop filters that define the
overall phase noise response of the closed loop and the
switching time in multi-channel PLLs.

Further tutorials with give an example of PLL switching
time and PLL phase noise performance.

5 REFERENCES
[1] Microwave and Wireless Synthesiser Theory and
Design Ulrich L Rohde, 1997, Wiley-Interscience,
ISBN 0-471-52019-5
[2] RF and Microwave Circuit Design For Wireless
communications, L E Larson, 1997, Artech House ISBN
0-89006-818-6, Chapter 6.
[3] Radio Frequency Design Wes Hayward, 1994, The
American Radio Relay League, ISBN 0-87259-492-0,
Chapter 7.
[4] Oscillator Design and Simulation, Randall W Rhea,
1995, Noble Publishing, ISBN 1-884932-30-4, p 35.