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HDL Program

The document describes a Verilog code to implement an up-down counter. It contains a module that defines the counter with inputs for a clock, reset, and signal a, and an output for the 5-bit counter value. The always block increments or decrements the counter value depending on the value of a on each clock edge, unless there is a reset. A test bench instantiates the counter module and provides a clock signal and toggles the reset and a signals to test the up and down counting.

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Pawan Rauniyar
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56 views

HDL Program

The document describes a Verilog code to implement an up-down counter. It contains a module that defines the counter with inputs for a clock, reset, and signal a, and an output for the 5-bit counter value. The always block increments or decrements the counter value depending on the value of a on each clock edge, unless there is a reset. A test bench instantiates the counter module and provides a clock signal and toggles the reset and a signals to test the up and down counting.

Uploaded by

Pawan Rauniyar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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Aim of experiment:-write a program in Verilog to implement counters.

Verilog code:-
module counter(a, clk, reset, out);
input a;
input clk;
input reset;
output [4:0]out;
reg[4:0]out;
alwas !(posedge clk)
"egin
if(reset##$)
out#%&"0;
else if(reset##0''a##$)
out#out($;
else if(reset##0''a##0)
out#out-$;
end
endmodule

Test bench
module updown)*;
++ ,nputs
reg a;
reg clk;
reg reset;
++ -utputs
wire [4:0] out;
++ ,nstantiate t.e /nit /nder 0est (//0)
counter uut (
1a(a),
1clk(clk),
1reset(reset),
1out(out)
);
initial
clk#$&"0;
alwas
2$ clk#3clk;
initial
"egin
reset #$;a#0;
2% reset#0;a#$;
2% reset#0;a#0;
2% 4stop;
end
endmodule

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