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8051 Instruction Set

The document describes the instruction set for the 8051 microcontroller. It contains a table listing the hex code, mnemonic, number of bytes, and operands for each instruction. The instructions include arithmetic, logic, branching, and data transfer operations for manipulating registers and memory on the 8051.

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anamika_2k8
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166 views6 pages

8051 Instruction Set

The document describes the instruction set for the 8051 microcontroller. It contains a table listing the hex code, mnemonic, number of bytes, and operands for each instruction. The instructions include arithmetic, logic, branching, and data transfer operations for manipulating registers and memory on the 8051.

Uploaded by

anamika_2k8
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLSX, PDF, TXT or read online on Scribd
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8051-Instruction Set

Hex Hex
Code Code
0 1
NOP
80
1 2
AJMP
addr11 81
2 3
LJMP
addr16 82
3 1
RR
A 83
4 1
INC
A 84
5 2
INC
direct 85
6 1
INC
@R0 86
7 1
INC
@R1 87
8 1
INC
R0 88
9 1
INC
R1 89
0A 1
INC
R2 8A
0B 1
INC
R3 8B
0C 1
INC
R4 8C
0D 1
INC
R5 8D
0E 1
INC
R6 8E
0F 1
INC
R7 8F
10 3
JBC
bit, offset 90
11 2
ACALL
addr11 91
12 3
LCALL
addr16 92
13 1
RRC
A 93
14 1
DEC
A 94
15 2
DEC
direct 95
16 1
DEC
@R0 96
17 1
DEC
@R1 97
18 1
DEC
R0 98
19 1
DEC
R1 99
1A 1
DEC
R2 9A
1B 1
DEC
R3 9B
1C 1
DEC
R4 9C
1D 1
DEC
R5 9D
1E 1
DEC
R6 9E
1F 1
DEC
R7 9F
20 3
JB
bit, offset A0
21 2
AJMP
addr11 A1
22 1
RET
A2
23 1
RL
A A3
24 2
ADD
A, #immed A4
25 2
ADD
A, direct A5
26 1
ADD
A, @R0 A6
27 1
ADD
A, @R1 A7
28 1
ADD
A, R0 A8
Bytes Mnemonic Operands
29 1
ADD
A, R1 A9
2A 1
ADD
A, R2 AA
2B 1
ADD
A, R3 AB
2C 1
ADD
A, R4 AC
2D 1
ADD
A, R5 AD
2E 1
ADD
A, R6 AE
2F 1
ADD
A, R7 AF
30 3
JNB
bit, offset B0
31 2
ACALL
addr11 B1
32 1
RETI
B2
33 1
RLC
A B3
34 2
ADDC
A, #immed B4
35 2
ADDC
A, direct B5
36 1
ADDC
A, @R0 B6
37 1
ADDC
A, @R1 B7
38 1
ADDC
A, R0 B8
39 1
ADDC
A, R1 B9
3A 1
ADDC
A, R2 BA
3B 1
ADDC
A, R3 BB
3C 1
ADDC
A, R4 BC
3D 1
ADDC
A, R5 BD
3E 1
ADDC
A, R6 BE
3F 1
ADDC
A, R7 BF
40 2
JC
offset C0
41 2
AJMP
addr11 C1
42 2
ORL
direct, A C2
43 3
ORL
direct, #immed C3
44 2
ORL
A, #immed C4
45 2
ORL
A, direct C5
46 1
ORL
A, @R0 C6
47 1
ORL
A, @R1 C7
48 1
ORL
A, R0 C8
49 1
ORL
A, R1 C9
4A 1
ORL
A, R2 CA
4B 1
ORL
A, R3 CB
4C 1
ORL
A, R4 CC
4D 1
ORL
A, R5 CD
4E 1
ORL
A, R6 CE
4F 1
ORL
A, R7 CF
50 2
JNC
offset D0
51 2
ACALL
addr11 D1
52 2
ANL
direct, A D2
53 3
ANL
direct, #immed D3
54 2
ANL
A, #immed D4
55 2
ANL
A, direct D5
56 1
ANL
A, @R0 D6
57 1
ANL
A, @R1 D7
58 1
ANL
A, R0 D8
59 1
ANL
A, R1 D9
5A 1
ANL
A, R2 DA
5B 1
ANL
A, R3 DB
5C 1
ANL
A, R4 DC
5D 1
ANL
A, R5 DD
5E 1
ANL
A, R6 DE
5F 1
ANL
A, R7 DF
60 2
JZ
offset E0
61 2
AJMP
addr11 E1
62 2
XRL
direct, A E2
63 3
XRL
direct, #immed E3
64 2
XRL
A, #immed E4
65 2
XRL
A, direct E5
66 1
XRL
A, @R0 E6
67 1
XRL
A, @R1 E7
68 1
XRL
A, R0 E8
69 1
XRL
A, R1 E9
6A 1
XRL
A, R2 EA
6B 1
XRL
A, R3 EB
6C 1
XRL
A, R4 EC
6D 1
XRL
A, R5 ED
6E 1
XRL
A, R6 EE
6F 1
XRL
A, R7 EF
70 2
JNZ
offset F0
71 2
ACALL
addr11 F1
72 2
ORL
C, bit F2
73 1
JMP
@A+DPTR F3
74 2
MOV
A, #immed F4
75 3
MOV
direct, #immed F5
76 2
MOV
@R0, #immed F6
77 2
MOV
@R1, #immed F7
78 2
MOV
R0, #immed F8
79 2
MOV
R1, #immed F9
7A 2
MOV
R2, #immed FA
7B 2
MOV
R3, #immed FB
7C 2
MOV
R4, #immed FC
7D 2
MOV
R5, #immed FD
7E 2
MOV
R6, #immed FE
7F 2
MOV
R7, #immed FF
2
SJMP
offset
2
AJMP
addr11
2
ANL
C, bit
1
MOVC
A, @A+PC
1
DIV
AB
3
MOV
direct, direct
2
MOV
direct, @R0
2
MOV
direct, @R1
2
MOV
direct, R0
2
MOV
direct, R1
2
MOV
direct, R2
2
MOV
direct, R3
2
MOV
direct, R4
2
MOV
direct, R5
2
MOV
direct, R6
2
MOV
direct, R7
3
MOV
DPTR, #immed
2
ACALL
addr11
2
MOV
bit, C
1
MOVC
A, @A+DPTR
2
SUBB
A, #immed
2
SUBB
A, direct
1
SUBB
A, @R0
1
SUBB
A, @R1
1
SUBB
A, R0
1
SUBB
A, R1
1
SUBB
A, R2
1
SUBB
A, R3
1
SUBB
A, R4
1
SUBB
A, R5
1
SUBB
A, R6
1
SUBB
A, R7
2
ORL
C, /bit
2
AJMP
addr11
2
MOV
C, bit
1
INC
DPTR
1
MUL
AB
reserved
2
MOV
@R0, direct
2
MOV
@R1, direct
2
MOV
R0, direct
Operands Bytes Mnemonic
2
MOV
R1, direct
2
MOV
R2, direct
2
MOV
R3, direct
2
MOV
R4, direct
2
MOV
R5, direct
2
MOV
R6, direct
2
MOV
R7, direct
2
ANL
C, /bit
2
ACALL
addr11
2
CPL
bit
1
CPL
C
3
CJNE
A, #immed, offset
3
CJNE
A, direct, offset
3
CJNE
@R0, #immed, offset
3
CJNE
@R1, #immed, offset
3
CJNE
R0, #immed, offset
3
CJNE
R1, #immed, offset
3
CJNE
R2, #immed, offset
3
CJNE
R3, #immed, offset
3
CJNE
R4, #immed, offset
3
CJNE
R5, #immed, offset
3
CJNE
R6, #immed, offset
3
CJNE
R7, #immed, offset
2
PUSH
direct
2
AJMP
addr11
2
CLR
bit
1
CLR
C
1
SWAP
A
2
XCH
A, direct
1
XCH
A, @R0
1
XCH
A, @R1
1
XCH
A, R0
1
XCH
A, R1
1
XCH
A, R2
1
XCH
A, R3
1
XCH
A, R4
1
XCH
A, R5
1
XCH
A, R6
1
XCH
A, R7
2
POP
direct
2
ACALL
addr11
2
SETB
bit
1
SETB
C
1
DA
A
3
DJNZ
direct, offset
1
XCHD
A, @R0
1
XCHD
A, @R1
2
DJNZ
R0, offset
2
DJNZ
R1, offset
2
DJNZ
R2, offset
2
DJNZ
R3, offset
2
DJNZ
R4, offset
2
DJNZ
R5, offset
2
DJNZ
R6, offset
2
DJNZ
R7, offset
1
MOVX
A, @DPTR
2
AJMP
addr11
1
MOVX
A, @R0
1
MOVX
A, @R1
1
CLR
A
2
MOV
A, direct
1
MOV
A, @R0
1
MOV
A, @R1
1
MOV
A, R0
1
MOV
A, R1
1
MOV
A, R2
1
MOV
A, R3
1
MOV
A, R4
1
MOV
A, R5
1
MOV
A, R6
1
MOV
A, R7
1
MOVX
@DPTR, A
2
ACALL
addr11
1
MOVX
@R0, A
1
MOVX
@R1, A
1
CPL
A
2
MOV
direct, A
1
MOV
@R0, A
1
MOV
@R1, A
1
MOV
R0, A
1
MOV
R1, A
1
MOV
R2, A
1
MOV
R3, A
1
MOV
R4, A
1
MOV
R5, A
1
MOV
R6, A
1
MOV
R7, A

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