NCV7728 Hex Half-Bridge Driver: W (Typ)

NCV7728
Hex Half-Bridge Driver

The NCV7728 is a Hex HalfBridge Driver with protection features
designed specifically for automotive and industrial motion control
applications. The NCV7728 has independent controls and diagnostics.
The device can be operated in forward, reverse, brake, and high
impedance states. The drivers are controlled via a 16 bit SPI interface
and are daisy chain compatible.
http://onsemi.com
Features
MARKING
DIAGRAM
Low Quiescent Current Sleep Mode

HighSide and LowSide Drivers Connected in a HalfBridge
Configuration
Integrated Freewheeling Protection (LS and HS)
0.55 A Peak Current
RDS(on) = 1 W (typ)
5 MHz SPI Control
Compliance with 5 V and 3. 3 V Systems
Undervoltage and Overvoltage Lockout
Discriminated Fault Reporting
Overcurrent Protection
Overtemperature Protection
Under Load Detection (HS and LS)
Daisy Chain Compatible with Multiple of 8 bit Devices
16Bit Frame Detection
These are PbFree Devices
SSOP24 NB
CASE 506AL
NCV7728
AWLYYWWG
NCV7728 = Specific Device Code

A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
Typical Applications
Automotive
Industrial
DC Motor Management for HVAC Application
Semiconductor Components Industries, LLC, 2014
March, 2014 Rev. 1
Publication Order Number:

NCV7728/D
NCV7728
Shown below is a typical application for the NCV7728 configuration.
MRA4003T3
Watchdog
13.2V
NCV7728
Power On
Reset
SO
SI
16Bit
Serial
Data
Interface
SCLK
CSB
uC
Logic
Control
Protection:
Under Load
Over Temperature
Under
voltage
Over
voltage
Over Current
VS1
VS2
GND
EN
GND
GND
High
Side
Switch
Voltage
Regulator
High
Side
Switch
High
Side
Switch
High
Side
Switch
High
Side
Switch
High
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
Low
Side
Switch
VCC
OUT1
OUT2
OUT3
OUT4
Figure 1. Typical Application
2
OUT5
OUT6
GND
NCV7728
VS1
DRIVE1
VS
EN
ENABLE
High Side
Driver
VS
Vcc
Vref1
BIAS
POR
Vref2
Fault
Reporting
Wave Shaping
OUT1
Control
Logic
Wave Shaping
VS
Low Side
Driver
SO
SPI
HS and LS Underload
16 Bit Logic
and Latch
Fault
SI
SCLK
Overcurrent
Thermal Warning &
Shutdown
CSB
VS
VS
DRIVE2
OUT
2
DRIVE3
OUT
3
DRIVE4
OUT4
DRIVE5
OUT
5
DRIVE6
OUT
6
VS1 & VS2
Vref1
Over Voltage
Lockout
VS
VS
VS1 & VS2
Vref2
Under Voltage
Lockout
VS
GND GND GND GND
VS2
Figure 2. Block Diagram
3
NCV7728
GND
24
GND
OUT1
2
3
23
22
OUT2
4
5
6
7
21
20
19
VS1
18
17
RESERVED
VS2
10
11
16
15
14
12
13
GND
OUT5
NC
SI
VCC
SO
EN
NC
OUT6
OUT4
GND
8
9
NC
SCLK
CSB
RESERVED
NC
OUT3
Figure 3. Pinout SSOP24
PACKAGE DESCRIPTION The pinout for the Hex HalfBridge in SSOP24 package is shown in the table below.
Pin #
SSOP24
Symbol
GND
Ground. Shorted to pin 24 internally.
OUT1
Half Bridge Output 1
OUT5
NC
No Connection. This pin should be isolated from any traces or via on the PCB board.
SI
Serial Input. 16 bit serial communications input. 3.3 V/5 V (TTL) Compatible. Internally pulled down.
VCC
SO
Serial Output. 16 bit serial communications output. 3.3 V/5 V Complaint
EN
Enable. Input high wakes the IC up from a sleep mode. 3.3 V/5 V (TTL) Compatible. Internally pulled down.
NC
10
OUT6
11
OUT4
12
GND
13
GND
14
OUT3
15
NC
16
VS2
Voltage Power Supply input for the Drivers 3, 4 and 6. This pin must be connected to VS1 externally.
17
Reserved
Reserved for internal use. This pin must be grounded.
18
Reserved
Reserved for internal use. This pin must be grounded.
19
CSB
Chip Select Bar. Active low serial port operation. 3.3V/5V (TTL) Compatible. Internally pulled up.
20
SCLK
Serial Clock. Clock input for use with SPI communication. 3.3 V/5 V (TTL) Compatible. Internally pulled
down.
21
VS1
Voltage Power Supply input for the Drivers 1, 2 and 5, all the predrivers and the charge pump. This pin
must be connected to VS2 externally.
22
NC
23
OUT2
24
GND
Description
Power supply input for Logic.
4
NCV7728
MAXIMUM RATINGS
Rating
Symbol
Power Supply Voltage (VS1, VS2)

(DC)
(AC), t < 500ms, Ivsx > 2A
Value
VsxdcMax
VSXac
Unit
V
0.3 to 40
1.0
Output Pin OUTx

(DC)
(AC), t< 500ms, IOUTx > 1.1A
(AC), t< 500ms, IOUTx < 1A
VoutxDc
VoutxAc
Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
VioMax
0.3 to 5.5
Output Current (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)
IoutxImax
2.0 to 2.0
Electrostatic Discharge, Human Body Model, VSx, OUTx (AECQ100002)
Vesd4k
4.0
kV
Electrostatic Discharge, Human Body Model, all other pins (AECQ100002)
Vesd2k
2.0
kV
0.3 to 40
1.0
1.0
Electrostatic Discharge, Machine Model (AECQ100003)
Vesd200
200
Short Circuit Reliability Characterization
AECQ10x
Grade A
Tj
40 to 150
Tstr
55 to 150
MSL2
Operating Junction Temperature

Storage Temperature Range
Moisture Sensitivity Level (MAX 260C Processing)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL INFORMATION (Note 1)

Rating
Symbol
Value
Unit
Junction to Ambient
RqJA
96.4
C/W
Junction to Lead
RyJL
63
C/W
1. Thermal Information is based on having 3 high side and 3 low side devices dissipating 80 mW each on a 2 layer board 0.062 thick FR4 board
with 600 mm2 copper spreader area. 2 oz copper is used for the copper spreader area and the ambient temperature is specified at 25C.
RECOMMENDED OPERATING CONDITIONS

Value
Symbol
Min
Max
Unit
Digital Supply Input Voltage
VccOp
3.15
5.25
Battery Supply Input Voltage
VsxOp
5.5
28
DC Output Current
IxOp
0.55
Junction Temperature
TjOp
40
125
Rating
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5
NCV7728
ELECTRICAL CHARACTERISTICS (40C < TJ < 150C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise
specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Supply Current (VS1 + VS2)

Sleep Mode
IqVsx85
VS1 = VS2 = 13.2 V, VCC = 0 V 40C to 85C

No Load
1.0
2.5
mA
Supply Current (VS1 + VS2)

Active Mode
IvsOp
EN = VCC, 5.5 V < VSx < 28 V No Load
2.5
5.0
mA
IqVCC
CSB = VCC, EN = SI = SCLK = 0 V

(40C to 85C)
EN = CSB = VCC, SI = SCLK = 0 V
No Load
1.0
2.5
mA
1.5
3.0
mA
Sleep Mode, 40C to 85C, No Load
mA
GENERAL
Supply Current (VCC)

Sleep Mode
Active Mode
Total Sleep Mode Current
I(VS1) + I(VS2) + I(VCC)
IVCCOp
IqTot
VCC PowerOnReset Threshold
VCCpor
VCC increasing
2.55
2.9
VSx Undervoltage Detection

Threshold
VsXuv
VSx decreasing
3.7
4.1
4.5
VSx Undervoltage Detection

Hysteresis
VsXuHys
100
450
mV
VSx Overvoltage Detection

Threshold
VsXov
32
36
40
VSx Overvoltage Detection

Hysteresis
VsXoHys
2.5
120
140
170
VSx increasing
THERMAL RESPONSE
Thermal Warning
Twr
Not ATE tested
TwHy
Not ATE tested
20
Tsd
Not ATE tested
150
175
200
TsdHy
Not ATE tested
20
RDSonHS
Iout = 500 mA
2.25
Output Low RDS(on) (sink)
RDSonLS
Iout = 500 mA
2.0
Output Path RDS(HSx+LSx)
RDSonPath
Iout = 500 mA
4.0
Source Leakage Current
IsrcLkg13.2
IsrcLkg40
OUT(16) = 0 V, VSx = 13.2 V, VCC = 5 V,

40C to 85C
OUT(16) = 0 V, VSx = 40 V, VCC = 5 V,
40C to 85C
1.0
mA
5.0
1.0
5.0
Thermal Warning Hysteresis

Thermal Shutdown
Thermal Shutdown Hysteresis
OUTPUTS
Output High RDS(on) (source)
Sink Leakage Current
IsnkLkg13.2
IsnkLkg40
OUT(16) = VSx = 13.2 V, VCC = 5 V,

40C to 85C
OUT(16) = VSx = 40 V, VCC = 5 V,
40C to 85C
mA
Overcurrent Shutdown Threshold (Source)
IsdSrc
VCC = 5 V, VSx = 13.2 V
2.0
1.2
0.8
Overcurrent Shutdown Threshold (Sink)
IsdSnk
VCC = 5 V, VSx = 13.2 V
0.8
1.2
2.0
10
25
50
ms
Over Current Delay Timer
TdOc
Under Load Detection Threshold (Low Side)
IuldLS
VCC = 5 V, VSx = 13.2 V
2.0
11
20
mA
Under Load Detection Threshold (High Side)
IuldHS
VCC = 5 V, VSx = 13.2 V
20
11
2.0
mA
Under Load Detection Delay

Time
TdUld
VCC = 5 V, VSx = 13.2 V
200
350
600
ms
6
NCV7728
ELECTRICAL CHARACTERISTICS (40C < TJ < 150C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise
specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
0.9
1.3
2.0
0.6
BODY DIODE
Power Transistor Body Diode
Forward Voltage
VbdFwd
If = 500 mA
LOGIC INPUTS (EN, SI, SCLK, CSB)

Input Threshold
High
Low
VthInH
VthInL
Input Hysteresis (SI, SCLK,

CSB)
VthInHys
50
150
300
mV
Enable Hysteresis
VthENHys
150
400
800
mV
EN = SI = SCLK = VCC
50
125
200
kW
CSB = 0 V
50
125
250
kW
Cinx
Not ATE tested
15
pF
Output High
VsoH
ISOURCE = 1 mA
VCC
0.6
Output Low
VsoL
ISINK = 1.6 mA
0.4
Input Pulldown Resistance

(EN, SI, SCLK)
Input Pullup Resistance
(CSB)
Input Capacitance
Rpdx
RpuCSB
LOGIC OUTPUT (SO)
Tristate Leakage
ItriStLkg
CSB = 5 V
mA
Tristate Output Capacitance
ItriStCout
CSB = VCC, 0 V < VCC < 5.25 V

Not ATE tested
15
pF
7
NCV7728
ELECTRICAL CHARACTERISTICS (40C < TJ < 150C, 5.5 V < VSx < 40 V, 3.15 < Vcc < 5.25 V, EN= Vcc, unless otherwise
specified)
Characteristic
Symbol
Conditions
Timing
Chart
Min
Typ
Max
Unit
DRIVER OUTPUT TIMING SPECIFICATIONS

High Side Turn On Time
ThsOn
VSx = 13.2 V, Rload = 39 W
7.5
13
ms
High Side Turn Off Time
ThsOff
VSx = 13.2 V, Rload = 39 W
3.0
6.0
ms
Low Side Turn On Time
TlsOn
VSx = 13.2 V, Rload = 39 W
6.5
13
ms
Low Side Turn Off Time
TlsOff
VSx = 13.2 V, Rload = 39 W
2.0
6.0
ms
High Side Rise Time
ThsTr
VSx =13.2 V, Rload = 39 W
4.0
8.0
ms
High Side Fall Time
ThsTf
VSx = 13.2 V, Rload = 39 W
2.0
4.0
ms
Low Side Rise Time
TlsTr
VSx = 13.2 V, Rload = 39 W
1.0
3.0
ms
Low Side Fall Time
TlsTf
VSx = 13.2 V, Rload = 39 W
1.0
3.0
ms
High Side Off to Low Side On

NonOverlap Time
ThsOffLsOn
VSx = 13.2 V, Rload = 39 W
1.5
ms
Low Side Off to High Side On

NonOverlap Time
TlsOffHsOn
VSx = 13.2 V, Rload = 39 W
1.5
ms
SERIAL PERIPHERAL INTERFACE

SCLK Frequency
Fclk
VCC = 5 V
VCC = 3.15 V
5.0
2.0
MHz
SCLK Clock Period
TpClk
VCC = 5 V
VCC = 3.15 V
200
500
ns
SCLK High Time
TclkH
85
ns
SCLK Low Time
TclkL
85
ns
SCLK Setup Time
TclkSup
3
4
85
85
ns
SI Setup Time
TsiSup
11
50
ns
SI Hold Time
TsiH
12
50
ns
TcsbSup
5
6
100
100
ns
CSB High Time (Note 2)
TcsbH
5.0
ms
SO enable after CSB falling

edge
TenSo
VCC = 5 V
200
ns
SO disable after CSB rising

edge
TdisSo
VCC = 5 V
200
ns
CSB Setup Time
SO Rise Time
TsoR
Cload = 40 pF
Not ATE tested
10
25
ns
SO Fall Time
TsoF
Cload = 40 pF
Not ATE tested
10
25
ns
SO Valid Time
TsoV
Cload = 40 pF
SCLK to SO 50%,
Not ATE tested
10
20
50
ns
EN Low Valid Time (Note 3)
TenL
VCC = 5 V
EN going low 50% to
OUTx turing off 50%
10
ms
TenHspiV
100
ms
Tsrr
150
ms
EN High to SPI Valid

SRR Delay Between Two
Consecutive Frame (Note 4)
2. This is the minimum time the user must wait between SPI commands.
3. This is the minimum time the user must wait before bringing EN up.
4. This is the minimum time the user must wait to send a SRR command between consecutive frames. If Tsrr time is not met the SRR request
is ignored.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8
NCV7728
ELECTRICAL CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
10%
LS Turn OFF
TlsOff
HsOn
90%
10%
HS Turn ON
ThsTr
90%
ThsOn
CSB
LS Turn On
TlsTf
90%
TlsOn
10%
HS Turn Off
ThsOff
LsOn
90%
10%
ThsTf
90%
ThsOff
CSB
Figure 4. Detailed Driver Timing
9
NCV7728
4
7
CSB
6
5
SCLK
CSB
SO
SI
12
SCLK
10
11
SO
Figure 5. Detailed SPI Timing
10
NCV7728
5.0
4.5
2.40
VSx = 13.2 V
ACTIVE MODE VCC CURRENT (mA)
IqTot, TOTAL SLEEP MODE CURRENT (mA)
TYPICAL PERFORMANCE GRAPHS
VCC = 3.15 V
4.0
3.5
3.0
VCC = 5.25 V
2.5
2.0
VCC = 5 V
1.5
1.0
0.5
VSx = 13.2 V
2.35
150C
2.30
125C
2.25
25C
2.20
2.15
40C
2.10
0
50 30 10
10
30
50
70
90
110 130 150
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (C)
Figure 6. IqTot vs. Temperature
Figure 7. I(VCC) Active Mode vs. V(VCC)

4.1
2.0
VSx = 13.2 V
I(OUTx) = 0.5 A
3.6
RDS(on) (W)
1.6
PATH RDS(on) (W)
1.8
HSx
1.4
1.2
LSx
1.0
VSx = 13.2 V
I(OUTx) = 0.5 A
3.1
2.6
HSx + LSx
2.1
1.6
1.1
0.8
0.6
50
50
100
0.6
50
150
50
100
150
TEMPERATURE (C)
Figure 8. RDS(on) vs. Temperature
Figure 9. RDS(on) vs. Temperature

2.0
1.2
IsdSrc, IsdSnk OVERCURRENT (A)
BODY DIODE FORWARD VOLTAGE (V)
TEMPERATURE (C)
If = 0.5 A
1.1
1.0
LSx
0.9
HSx
0.8
50
5.5
VCC VOLTAGE (V)
50
100
1.5
0.5
0
VS = 13.2 V
VCC = 5.0 V
0.5
1.0
1.5
2.0
50
150
LSx
1.0
HSx
0
50
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Body Diode vs. Temperature
Figure 11. Overcurrent vs. Temperature
11
150
NCV7728
IsrcLkg, IsnkLkg LEAKAGE CURRENT (mA)
TYPICAL PERFORMANCE GRAPHS
0.2
HSx
0
LSx
0.2
0.4
VSx = 13.2 V
0.6
0.8
1.0
50
50
100
TEMPERATURE (C)
Figure 12. SourceSink Leakage vs.

Temperature
12
150
NCV7728
OPERATING DESCRIPTION
General Overview
SPI Communication
The NCV7728 is comprised of twelve DMOS power

drivers (six PMOS High Side Driver and six NMOS Low
Side Driver) configured as six half bridges that enables three
independent Full Bridge operations. Each output drive is
characterized for a max 550 mA DC load and has a typical
2 A surge capability (at VSx =13.2 V). Strict adherence to
integrated circuit die temperature is necessary. Maximum
die temperature is 150C. This may limit the number of
drivers enabled at one time. Output drive control and fault
reporting is handled via the SPI (Serial Peripheral Interface)
port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. An internal pull
down resistor is provided on the EN input to ensure the
device is off if the input signal is lost. Deasserting the EN
signal clears all the registers and resets the driver. When the
EN signal is asserted the IC will proceed with the VCC POR
cycle and brings the drivers into normal operation.
16bit full duplex SPI communication has been

implemented for the communication of this IC for device
configurations, driver controls and reading the diagnostic
data. In addition to the 16bit diagnostic data, a pseudo bit
(PRE_15) can also be retrieved from the SO register. The
part is required to be enabled (EN active high) for SPI
communication. The inputs for the SPI are TTL logic
compatible and are specified by the VthInH and VthInL
thresholds. The active low CSB input has a pull up resistor
and the remaining SPI inputs have pulldown resistors to
bias them to a known state when SPI is not active.
Reference the SPI communication frame format diagram
in Figure 13 for the 16 bit SPI implementation. Tables 1
and 2 define the programming bits and diagnostic bits
shown in Figure 13.
SPI COMMUNICATION FRAME FORMAT
CSB
SSR
SI
SCLK
15
HBSEL
14
ULD
HBEN6 HBEN1
HBCNF6 HBCNF1
OVLO
13
SO
TSD
OCS
PSF
HBx[1:0]
ULD
TW
Figure 13. SPI Communication Frame Format
Communication is implemented as follows and is also illustrated in Figure 17:

1. SI and SCLK are set to low before the CSB cycle.
2. CSB goes low to allow serial data transfer.
3. SI data starting with the Most Significant bit (MSB) is shifted in first.
4. SI data is recognized on every falling edge of the clock.
5. Simultaneously, SO data from the previous frame starting with the MSB bit is shifted out on every rising edge of the
clock.
6. The input data is compared to a 16 bit counter for the initial 16 bits shifted into SI for frame detection error scheme.
7. The sequential input bits are compared to a n x 8 (n can take on the value of any integer) bit counter for daisy chain
operations and are monitored by the frame detection error scheme.
8. CSB goes high and the most recent 16 bits clocked into SI are transferred to the data register given that there is no
frame detection error. Otherwise the entire frame is ignored.
9. SO is tristate when CSB is high.
13
NCV7728
Table 1. SPI INPUT DATA FRAME
Input Data
Bit Number
Bit Name
Bit Description
Bit Status
15
SRR
Status Reset Register

When Asserted All Latched Faults are Cleared (TSD, OCS & ULD)
0 = No Reset
Half Bridge Selection
1 = Reset
14
HBSEL (Note 5)
Reserved
13
ULDSC
Under Load Detection Shutdown Control

Global Enable; Per Half Bridge Operation
0 = Disable
12
HBEN6
Half Bridge 6 Enable
0 = High Z
1 = Enable
1 = Enabled
11
HBEN5
0 = High Z
1 = Enabled
10
HBEN4
HBEN3
0 = High Z
1 = Enabled
0 = High Z
1 = Enabled
HBEN2
0 = High Z
1 = Enabled
HBEN1
HBCNF6
0 = High Z
1 = Enabled
Half Bridge 6 Configuration Control
0 = LS6 ON & HS6 OFF

1 = LS6 OFF & HS6 ON
HBCNF5

HBCNF4
HBCNF3

HBCNF2

HBCNF1

OVLO
Over Voltage Lock Out

Global Effect
0 = Disable
1 = Enable
5. HBSEL enables bridge selection for the NCV7719 and NCV7720 devices. In the NCV7728 it is recommended to set the HBSEL to zero.
14
NCV7728
Table 2. SPI OUTPUT DATA FRAME
Output Data
Bit Number
Bit Name
Bit Description
Bit Status
PRE_15
TSD
Latched Thermal Shutdown
OCS
Over Current Shutdown

Global Notification
0 = No Fault
15
PSF
Power Supply Failure on VS1 and/or VS2

Under Voltage and Over Voltage Monitoring
0 = No Fault
14
ULD
Under Load Detection

Global Notification
0 = No Fault
13
12
HB6
[1:0]
Half Bridge 6 Status
HB5
[1:0]
HB4
[1:0]
HB3
[1:0]
HB2
[1:0]
HB1
[1:0]
TW
Thermal Warning
Global Notification
0 = No Fault
11
10
9
8
7
6
5
4
3
2
1 = Fault
1 = Fault
1 = Fault
1 = Fault
0x00b Output Disable

0x01b OCS
0x10b ULD
0x11b Output Enabled
0 = No Fault
1 = Fault
HBx[1:0] bits are priority encoded to provide the status information of each of the half-bridge outputs. Figure 14 shows the
priority encoding state diagram for the HBx[1:0] bits.
15
NCV7728
HBENx= 0 or
Power On Reset
Under
Load
Output Enabled
11
HBENx= 1
Output Disabled
00
(default
)
ULD
10
Over
Current
OCS
01
SRR = 1 or
Power On Reset
Figure 14. SO HBx[1:0] Priority Encoding State Diagram
HBx[1:0] bits are priority encoded to provide the status

As seen from Figure 14 an over current event following an
information of each of the halfbridge outputs. Thus an over
under load condition on the same half-bridge reports HBx =
current shutdown fault must be cleared before an under load
10 then HBx = 01. However, an over current preceding
fault is reported on the same halfbridge. The latched
an under load fault only reports HBx = 01 since there are
thermal shutdown (TSD) information is available on SO
no direct path from the OCS state to the ULD state. Thus an
after CSB goes low until the first rising SCLK edge. The
over current shutdown fault must be cleared before an under
following procedures must be met for a true TSD reading:
load fault is reported on the same half-bridge.
1. SCLK and SI are low before the CSB cycle. Violating these conditions will results in an undetermined SPI behavior
or/and an incorrect TSD reading.
2. CSB transitioning from high to low.
3. CSB setup time (TcsbSup) is satisfied and the data is captured before the first SCLK rising edge.
16
NCV7728
Driver Control
The NCV7728 has the flexibility of controlling each

driver through the 16 bit SPI frame (Bits 121) and the logic
combination required for bridge control is defined in

Figure 15.
VS
HBCNFx
HSx
HBENx
OUTx
LSx
HBENx
HBCNFx
OUTx
OUTx in High Impedance State
HSx Off and LSx On
HSx On and LSx Off
X = Dont Care
Figure 15. Bridge Control Logic

Daisy Chain Operation
The digital design insures that the high side and low side
of the same half bridge will not be active at the same time.
Thus the device self protects from a current shoot through
condition. Delays (ThsOffLsOn and TlsOffHsOn) between
the high side and low side switching are implemented for
same reasons.
Daisy chain communications between multiple of 8bit

SPI compatible ICs is possible by connection of the serial
output pin (SO) to the input of the sequential IC (SI). The
clock phase and clock polarity respect to the data must be the
same for all the devices on the chain. Figure 16 illustrates the
hardware configuration of NCV7728 daisy chained with a
n*8 bit (ie n = 2; 16 bit) SPI device. The progression of data
from the MCU through the sequential devices is also shown.
Strict adherence to the frame format illustrated in Figure 17
is required for the proper serial daisy chain operations.
Frame Detection
To maintain the data integrity, the NCV7728 has 16 bit

frame detection. A valid frame for a single CSB cycle
requires 16 bits to be clocked into SI for the initial 16 bits and
n x 8 bits thereafter. In an instance of an invalid SPI frame
the entire frame is ignored, but the previous states of the
corresponding outputs are maintained.
17
NCV7728
MCU
NCV7728
16 Bit SPI
n*8 Bit SPI Device

(ie n=2; 16 bits)
CSB
CSB
SCLK
MI
CSB
SCLK
SCLK
MO
8 bits
8 bits
8 bits
8 bits
Command Bits for the Device 2

Previous Diagnostic Bits from Device2
Command Bits for Device 1
Previous Diagnostic Bits From Device1
SI
8 bits
8 bits
8 bits
8 bits
SO
Device1
8 bits
8 bits
8 bits
8 bits
SI
SO
Device2
Figure 16. Serial Daisy Chain
detection counters. For these scenarios, invalid data is

accepted by NCV7728 and possibly by other devices on the
chain depending on their frame detection design. The data
shifted in will be transferred to the data registers of the
devices on the beginning of the chain and the devices at the
end of the chain will get the previous diagnostic data of the
preceding devices.
If Device 2 is a 16 bit IC, then a total of 32 bits must be

generated from the MCU for a complete transport of data in
the system. Monitoring of all the devices in the serial chain
must be employed on a system level architecture. Thus,
precautious measure should be taken to avoid situations
where not enough frames were sent to the devices, but the
frames transmitted did not violate the internal frame
18
NCV7728
24 bit Frame
Word B 8 bits
Word A 16 bits
CSB
SCLK
MSB
SI
15
LSB
MSB
LSB
LSB
MSB
LSB
SI data is recognized on the falling SCLK edge

.
SO
TSD
MSB
SO data is shifted out on the rising SCLK edge

.
Modulo16 counter begins on the first rising SCLK edge after CSB goes. low
Modulo16 counter ends 16 bit word length valid
.
Modulo8 counter begins on the next rising SCLK edge
.
Modulo8 counter ends 8 bit word length validValid n*8 bit frame.
.
Figure 17. SPI Data Recognition and Frame Detection
The TSD bit is multiplexed with the SPI SO data and ORd
with the SI input (Figure 18) to allow for reporting in a serial
daisy chain configuration in devices with the same SPI
protocol. A TSD error bit as a 1 automatically propagates
through the serial daisy chain circuitry from the SO output
of one device to the SI input of the next. This is shown in

Figures 19 and 20; first as the daisy chained devices
connected with no thermal shutdown latched fault
(Figure 19) and subsequently with a TSD fault in device 1
propagating through to device 2 (Figure 20).
SO
TSD
SO
SI SPI
S
Figure 18. TSD SPI Link

SI
SO
SI
TSD
NCV7718 0 Device #1
SI
SO
SO
Figure 19. Daisy Chain No TSD Fault
SO
1
TSD
NCV7718 1 Device #1
TSD
NCV7718 0 Device #2
SI
1
TSD
NCV7718 0 Device #2
Figure 20. Daisy Chain TSD Error

Propagation
19
NCV7728
DEVICE PROTECTION, DIAGNOSTICS AND FAULT REPORTING
Power Up/Down Control
Under Voltage Shutdown
Each analog power pin (VS1 or VS2) powers their

respective output drivers. After a device has powered up and
the output drivers are allowed to turn on, the output drivers
will not turn off until the voltage on the supply pins is
reduced below the initial under voltage threshold, exceeds
the over voltage threshold or if shut down by either a SPI
command or a fault condition.
Internal powerup circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. All the internal counters, SI and SO along
with all the digital registers will be cleared on VCC POR.
Exceeding the under voltage lockout threshold on VCC
allows information to be input through the SPI port for turn
on control. Logic information remains intact over the entire
VS1 and VS2 voltage range.
An under voltage lockout circuit prevents the output

drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2 and
VCC pins. A builtin hysteresis on the under voltage
threshold is included to prevent an unknown region on the
power pins; VCC, VS1 and VS2. When the VCC goes below
the threshold, all outputs are turned off and the input and
output registers are cleared.
An under voltage condition on the VSx pins will result in
shutting off all the drivers and the status bit 14 (PSF) will be
set. The SPI port remains active during a VSx undervoltage
if proper VCC voltage is supplied. Also all driver states will
be maintained in the logic circuitry with the valid VCC
voltage. Once the input voltage VSx is above the under
voltage threshold level the drivers will return to
programmed operation and the PSF output register bit is
cleared.
Undervoltage timing diagram is provided in Figure 21.
SI
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
HS
OUTx
HS
OUTx
HS
SO
No
Fault
PSF
No
Fault
0x00
No
Fault
Status
No Fault
PSF
No
Fault
Output
State
OUTx GND
ALL
Z
OUTx GND
ALL
Z
0x00
No
Fault
OUTx VS
VSx
VSUV
Vcc
VccUV
t
Figure 21. UnderVoltage Timing Diagram
20
NCV7728
Over Voltage Shutdown
reestablished, the programmed outputs will turn back on.

Overvoltage shutdown can be disabled by using the SPI
input bit 0 (OVLO = 0) to run through a load dump situation.
It is highly recommended to operate the part with OVLO bit
asserted to ensure that the drivers remain off during a load
dump scenario.
The table below describes the driver status when
enabling/disabling the over voltage lock out feature during
normal and overvoltage situations.
Over voltage shutdown circuitry monitors the voltage on

the VS1 and VS2 pins, which permits a 40 V maximum.
When the Overvoltage Threshold level has been breached
on the VS1or VS2 supply input, the output bit 14 (PSF) will
be set. Additionally, if the input bit 0 (OVLO) is asserted, all
outputs will turn off. During an Over Voltage Lockout
condition the turn on/off status is maintained in the logic
circuitry. When proper input voltage levels are
Table 3. OVERVOLTAGE LOCK OUT (OVLO)
OVLO Input
Bit
VSx OVLO
Condition
Output Data Bit 14 Power Supply Fail (PSF) Status
OUTx Status
Not in Overvoltage Outputs Unchanged
1
(Clears when VSx within Operating Range)
In Overvoltage Outputs Unchanged
Not in Overvoltage Outputs Unchanged
1
(Clears when VSx within Operating Range)
All Outputs Off (Remain off until VSx is out

of OVLO)
Overvoltage timing diagram is provided in Figure 22.

SI
OUTx ON
OVLO=0
OUTx
ON
OUTx
ON
OUTx ON
OVLO=1
OUTx
ON
OUTx
OFF
SO
No
Fault
PSF
No
Fault
PSF
No
Fault
No
Fault
PSF
No
Fault
PSF
No
Fault
No
Fault
ALL
Z
OUTx
ON
OUTx Z
Status
Output
State
VSx
OUTx
ON
VSOV
VSOV
t
Figure 22. OverVoltage Timing Diagram
21
NCV7728
Over Current Detection and Shutdown
command. The event triggering the over current shutdown

condition must be resolved prior to clearing the OCS bit to
avoid repetitive stress on the drivers. Failure to do so may
result in non reversible fatal damage.
The SO data OCS shown on Figure 23 corresponds to both
the global SO bit #15 and the HBx OCS encoding state 01.
Note: high currents could cause a high rise in die
temperature. Devices will turn off if the die temperature
exceeds the thermal shutdown temperature.
The NCV7728 offers over current shutdown protection on

the OUTx pins by monitoring the current on the high side
and low side drivers. If the over current threshold is
breached, the corresponding output is latched off (HS and
LS driver is latched off) after the specified shutdown time,
TdOc. Upon over current shutdown, the serial output bit
OCS will be set and the corresponding HBx[1:0] will be
changed to 01 to denote a high power dissipation state.
Devices can be turned back on via the SPI port once the OCS
condition is cleared by setting the SRR to 1 on the next SPI
SI
OUTx ON
SRR=0
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx
ON
OUTx
ON
SO
No
Fault
No
Fault
OCS
OCS
No
Fault
OCS
Status
No
Fault
OCS
No
Fault
OCS
Output
State
OUTx
ON
OUTx Z
OUTx
ON
OUTx Z
TdOc
Output
Current
TdOc
IsdSxx
t
Figure 23. OverCurrent Timing Diagram

Under Load Detection
Control (ULDSC bit # 13) input bit is set then the offending
halfbridge output will be turned off (HS and LS drivers will
be latched off). Otherwise the outputs remain active and the
device configuration can be changed. The SO reporting is
stored until the SRR clears the fault. Since an OCS fault has
a higher priority over an under load fault, the HBx[1:0]
under load fault state can be masked by an over current fault.
There is only one global under load timer for all the
drivers. If the TdUld timer is already activated due to one
under load, any subsequent under load delays will be the
remainder of the TdUld timer.
The underload detection is employed on both the HS and

LS drivers. A global output bit (ULD) reports under load
fault if at least one of the channels detect an under load
condition. When configured for either LS or HS operation,
a minimum load current (IuldLS or |IuldHS| this is the
maximum open circuit detection threshold) is required when
the drivers are turned on to avoid an underload condition.
If the underload detection threshold has been breached
longer than the specified underload timer (TdUld), the
ULD output bit is set to 1 and HBx[1:0] bits transitions to
10. Furthermore, if the UnderLoad Detection Shutdown
Table 4. UNDERLOAD DRIVER STATUS
ULDSC Input
Bit 13
OUTx ULD
Condition
Output Data Bit Under Load Detect Status
OUTx Status
Unchanged
1
(Need SRR to reset)
Unchanged
Unchanged
1 (Need SRR to reset)
OUTx Latches off (Need SRR to reset)
The ULD SO data provided in the under load timing diagram in Figure 24 reflects the global ULD SO bit #13 and the HBx
ULD encoding state 10.
22
NCV7728
SI
LSx ON
ULDSC
=0
LSx
ON
LSx ON
SRR=1
LSx ON
ULDSC
=1
LSx ON
SRR=1
LSx
ON
HSx ON
ULDSC
=0
HSx ON
SRR=1
HSx ON
ULDSC
=1
SO
No
Fault
No
Fault
ULD
ULD
ULD
No
Fault
No
Fault
ULD
ULD
Status
Output
State
No Fault
ULD
OUTx
ON
No
Fault
OUTx
Z
OUTx GND
TdUld
No Fault
ULD
TdUld
Output
Current
ULD
OUTx GND
No
Fault
OUTx
Z
OUTx VS
TdUld
TdUld
TdUld
IuldLS
0A
t
IuldHS
Figure 24. LS Underload Timing Diagram

Thermal Warning and Thermal Shutdown
thermal sensors detects a thermal shutdown level then the

drivers on the offending half bridge are latched off. The TSD
(PRE_15) bit is set to capture a thermal shutdown event. A
valid SPI command with SRR and temperature below the
Tsd threshold are required to clear the latched fault. Since
thermal warning precedes an over temperature shutdown,
software polling of this bit will allow load control and
possible prevention of over temperature shutdown
conditions.
The NCV7728 provides individual thermal sensors for

each halfbridge. Moreover, the sensor reports over
temperature warning level and an over temperature
shutdown level. The TW status bit (output bit 0) will be set
if the temperature exceeds the over temperature warning
level, but the drivers will remain active. Once the IC
temperature fall below the thermal warning threshold the
TW flag is automatically clearly. If any of the individual
SI
OUTx
ON
OUTx
ON
OUTx
ON
OUTx
ON
OUTx ON
SRR=1
OUTx ON
SRR=1
SO
No
Fault
TW
No
Fault
TW
TSD
TW
TW
Status
No
Fault
TW
No
Fault
TW
TSD
TW
Output
State
TW
OUTx Z
OUTx ON
TW
OUTx
ON
TJ
TSD
TsdHy
TWR
TwHy
t
Figure 25. Thermal Warning and Shutdown Timing Diagram
23
NCV7728
Thermal Performance
160
1.6
150
1.4
qJA (C/W)
130
MAX POWER (W)
140
1 oz
120
110
2 oz
100
90
2.0 oz
1.2
1.0
1.0 oz
0.8
0.6
0.4
80
0.2
70
60
0
100
200
300
400
500
600
700
800 900
100
COPPER HEAT SPREADER AREA (sq mm)
R(t) (C/W)
10
300
400
500
600
700
COPPER HEAT SPREADER AREA
Figure 26. qJA vs. Cu Area
100
200
800 900
(mm2)
Figure 27. Power vs. Cu Area
Duty = 50%
25%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 28. R(t) vs. Duty Cycle
24
10
100
1000
NCV7728
Fault Handling
that is locked out during a fault conditions auto recovers to

the previous programmed state when the fault is resolved. A
latched fault flag on the serial output doesnt always
translate an output latched off fault.
The summary of all fault conditions, the driver status and
the clear requirements are provided in Table 5.
At an event of a driver latched off fault, the offending

halfbridge driver is disabled and the halfbridge
configuration is defaulted to zero (HBENx =0, HBCNFx =
0). The user is required to clear the output register fault and
to resend the proper SPI frame to turn on the drivers. A driver
Table 5. FAULT SUMMARY
Driver
Condition after Parameters
Within Specified Limits
Fault Memory
Serial Output Bit
Driver
Condition During Fault
Under Load
(ULDSC = 0)
Latched
Outputs Unchanged.
Allowed to turn/ remain on
Allowed to turn/remain on
Valid SPI frame with

SRR set to 1
Under Load
(ULDSC = 1)
Latched (Note 6)
Offending HalfBridge is
Latched Off (LS and HS)
Latched Off
(LS and HS)

SRR set to 1
Over Current
Latched (Note 6)
Offending Output is
Latched Off
(LS and HS)
Offending Output is Latched

Off
(LS and HS)

SRR set to 1
NonLatched
Outputs Unchanged.
Allowed to turn/ remain on
provided that device is not
in thermal shutdown
Temp below (thermal

warning temp
hysteresis)
Thermal Shutdown
Latched (Note 6)
Offending HalfBridge
Drivers are Latched Off
(LS and HS)
Latched Off (LS and HS)

SRR set to 1.
Temperature blow
(thermal shutdown
hysteresis)
VS Power Supply
Fail (OverVoltage:
OVLO = 0)
NonLatched
Outputs Unchanged.
Allowed to
turn/ remain on
VS below (Over Voltage

Threshold hysteresis)
VS Power Supply
Fail (OverVoltage:
OVLO = 1)
NonLatched
All Drivers are Locked

Out.
Outx High Z
Previous HalfBridge status

and driver configuration is
maintained. Allowed to
turn/remain on
Auto Recovers if the VS

voltage is below
overvoltage threshold
VS Power Supply
Fail (Under
Voltage)
NonLatched
All Drivers are Locked

Out.
Outx High Z
Previous HalfBridge status

and driver configuration is
maintained. Allowed to
turn/remain on
Auto Recovers if the VS

voltage is above the
Under Voltage
threshold
Fault
Thermal Warning
Output Register Clear

Requirement
6. Latched conditions are cleared via the SPI SRR input bit = 1, by cycling the EN pin or with a poweron reset of VCC.
25
NCV7728
APPLICATION DIAGRAM
The application drawing below demonstrates the drive
capability of the NCV7728. The VS1 and VS2 pins must be
tied together to avoid any potential difference in the supply

voltage.
MRA4003T3
13.2V
0.1uF
VS1
VS2
VIN
20k
VCC
VOUT
EN
NCV8518B
1.0uF
DELAY
120k
OUT1
GND
WDI
RESET
M1
OUT2
M5
OUT3
NCV7728
IO
RESET
M2
OUT4
Hex Half Bridge
M4
VCC
OUT5
M3
MOSI
MISO
SO
SCLK
SCLK
CSB
uC
SI
CSB
EN
OUT6
EN
GND GND GND GND
Figure 29. Application Drawing
ORDERING INFORMATION
Device
NCV7728DPR2G
Package
Shipping
SSOP24
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
26
NCV7728
PACKAGE DIMENSIONS
SSOP24 NB
CASE 565AL
ISSUE O
0.20 C D
D
A
13
24
0.20 C D
L2
2X
E1
PIN 1
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 PER SIDE.
DIMENSION E1 DOES NOT INLCUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
2X
L
C
DETAIL A
12
24X
TOP VIEW
GAUGE
PLANE
SEATING
PLANE
0.25 C D
b
0.25
2X 12 TIPS
M
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
M
C A-B D
A2
h
x 45
0.10 C
M
0.10 C
24X
SIDE VIEW
A1
SEATING
PLANE
END VIEW
DETAIL A
MILLIMETERS
MIN
MAX
1.75
1.35
0.10
0.25
1.25
1.50
0.20
0.30
0.19
0.25
8.65 BSC
6.00 BSC
3.90 BSC
0.65 BSC
0.22
0.50
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
24X
24X
0.42
24
1.12
13
6.40
12
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLCs product/patent coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION

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27
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NCV7728/D

NCV7728 Hex Half-Bridge Driver: W (Typ)

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NCV7728

Hex Half-Bridge Driver

Low Quiescent Current Sleep Mode

NCV7728 = Specific Device Code

Semiconductor Components Industries, LLC, 2014

March, 2014 Rev. 1

Publication Order Number:

Figure 1. Typical Application

VS1 & VS2

GND GND GND GND

Figure 2. Block Diagram

Figure 3. Pinout SSOP24

Ground. Shorted to pin 24 internally.

Half Bridge Output 1

Half Bridge Output 5

Serial Output. 16 bit serial communications output. 3.3 V/5 V Complaint

Half Bridge Output 6

Half Bridge Output 4

Ground. Shorted to pin 13 internally.

Ground. Shorted to pin 12 internally.

Half Bridge Output 3

Reserved for internal use. This pin must be grounded.

Reserved for internal use. This pin must be grounded.

Half Bridge Output 2

Ground. Shorted to pin 1 internally.

Power supply input for Logic.

Power Supply Voltage (VS1, VS2)

Output Pin OUTx

Output Current (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6)

Electrostatic Discharge, Human Body Model, VSx, OUTx (AECQ100002)

Electrostatic Discharge, Human Body Model, all other pins (AECQ100002)

Electrostatic Discharge, Machine Model (AECQ100003)

Short Circuit Reliability Characterization

Operating Junction Temperature

THERMAL INFORMATION (Note 1)

RECOMMENDED OPERATING CONDITIONS

Digital Supply Input Voltage

Battery Supply Input Voltage

Supply Current (VS1 + VS2)

VS1 = VS2 = 13.2 V, VCC = 0 V 40C to 85C

Supply Current (VS1 + VS2)

EN = VCC, 5.5 V < VSx < 28 V No Load

CSB = VCC, EN = SI = SCLK = 0 V

Sleep Mode, 40C to 85C, No Load

Supply Current (VCC)

VCC PowerOnReset Threshold

VSx Undervoltage Detection

VSx Undervoltage Detection

VSx Overvoltage Detection

VSx Overvoltage Detection

Not ATE tested

Not ATE tested

Not ATE tested

Not ATE tested

Output Low RDS(on) (sink)

Output Path RDS(HSx+LSx)

Source Leakage Current

OUT(16) = 0 V, VSx = 13.2 V, VCC = 5 V,

Thermal Warning Hysteresis