NMOS Physical Structure

Source (S)
W

Gate (G)

eta
M

Drain (D)
p

n+

1111111111111
0000000000000
Polysilicon
1111111111111
0000000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000
11111111111
00000000000
l
1111111111111
0000000000000
11111111111
00000000000
L
1111111111111
0000000000000
11111111111
00000000000
eta
1111111111111
0000000000000
11111111111
00000000000
M
1111111111111
0000000000000
11111111111
00000000000
1111111111111
0000000000000

n+
Body (B)

CMOS Physical Structure

Cross-section

NMOS
S
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
SiO2
1111
0000
1111
0000
1111
0000
1111
0000

n+

G
11111111
00000000

PMOS
D

n+

D
11111111
00000000
11111111
00000000
11111111
00000000
11111111
00000000
11111111
00000000
11111111
00000000
SiO2
11111111
00000000
11111111
00000000
11111111
00000000
11111111
00000000

p+

G
11111111
00000000

nwell

S
11111
00000
11111
00000
11111
00000
11111
00000
11111
SiO2
p+ 00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000

Physical Operation

NMOS

VGS
S

VGS > Vtn

111111111111
000000000000

n+

n+

VDS = 0

VGS
S

VDS
G

VGS > Vtn

111111111111
000000000000

n+

n+

VDS : very small

Physical Operation

NMOS

VGS
S

VDS
G

VDS < Vov

111111111111
000000000000

n+

n+

Vov = VGS Vtn

VGS
S

VDS
G

n+

VGS > Vtn

VDS > Vov

111111111111
000000000000

VGS > Vtn

n+

Vov = VGS Vtn

ID-VDS Characteristics

NMOS

ID
VDS <Vov VDS >Vov
Triode
Active
VGS4
VGS3

ID
VDS
VGS

VGS2
VGS1

VDS

ID-VSD Characteristics

PMOS

ID
VSD <Vov VSD >Vov
Triode
Active
VSG4
VSG3
VSG
VSD
ID

VSG2
VSG1

VSD

NMOS DC Operation

Cuto: VGS < Vtn , ID = 0

D
IG =0

Triode (linear) region: VDS < Vov

ID

VGS
S
Vov = VGS Vtn

V
ID = k n
ov VDS

2
VDS

Active (saturation) region: VDS > Vov

ID =

kn W 2
Vov
2 L

PMOS DC Operation

Cuto: VSG < |Vtp| , ID = 0

S
VSG
ID

G
IG =0

Triode (linear) region: VSD < Vov

D
Vov = VSG |Vtp|

V
ID = k p
ov VSD

2
VSD

Active (saturation) region: VSD > Vov

ID =

kp W 2
Vov
2 L

MOSFET DC Biasing

Resistive

VDD
RG1

RG2

VDD
RD

V2

RG1

RS

RG2

VSS

V2 =

V1 =

RG1 + RG2

V2 = VGSn + RSIDn
IDn =

2 L

RD
VSS

RG2(VDD + VSS)

kn W

RS

V1

RG1(VDD + VSS)
RG1 + RG2

V1 = VSGp + RSIDp
2

(VGSn Vtn)

IDp =

kp W
2 L

(VSGp Vtp)2
9

MOSFET DC Biasing

NMOS Current Mirror

Assuming VGS1 > Vtn

VGS1 = VDS1 VDS1 > VGS1 Vtn
M1 is ACTIVE

kn W

ID1 =
(VGS1 Vtn)2

2 L 1

ID1
M1

ID2
M2

Assuming M2 is ACTIVE

k W
ID2 = n (VGS2 Vtn)2

2 L 2
Since VGS1 = VGS2

ID1
L
= W 1

ID2

L 2
10

NMOS Current Mirror

Example

VDD

R
ID1

ID2

ID3

ID4

ID5

ID6

M1
10/0.5

M2
2/0.5

M3
20/0.5

M4
5/0.5

M5
30/0.5

M6
15/0.5

VSS

11

NMOS Current Mirror

Example

VDD + VSS = R1ID1 + VGS1

ID1 =

kn 10
2 0.5

(VGS1 Vtn)2

Find ID1

Assuming that all transistors are ACTIVE:

ID2 =

ID1
5

ID5 = 3ID1

ID3 = 2ID1
ID6 =

3
2

ID4 =

ID1
2

ID1

12

MOSFET DC Biasing

PMOS Current Mirror

Assuming VSG1 > |Vtp|

VSG1 = VSD1 VSD1 > VSG1 |Vtp|

M1
ID1

M2
ID2

M1 is ACTIVE

kp W

ID1 =
(VSG1 |Vtp|)2

2 L 1
Assuming M2 is ACTIVE

k W
ID2 = p (VSG2 |Vtp|)2

2 L 2
Since VSG1 = VSG2

ID1
L
= W 1

ID2

L 2
13

PMOS Current Mirror

Example

VDD
M1
10/1

M2
20/1

ID1

ID2

M3
2/1
ID3

M4
5/1
ID4

M5
40/1

M6
30/1

ID5

ID6

VSS

14

PMOS Current Mirror

Example

VDD + VSS = R1ID1 + VSG1

ID1 =

kp 10
2

(VSG1 |Vtp|)2

Find ID1

Assuming that all transistors are ACTIVE:

ID1

ID2 = 2ID1

ID3 =

ID5 = 4ID1

ID1

ID6 = 3ID1

ID4 =

15

Current Mirror Biasing

Example 1

VDD
M8
10/0.5
R
VI
M1
10/1

M3
15/1

M2
20/1

M5
5/0.5 VB
M4
30/1

M10
5/0.5

M12
20/0.5

M7
5/1
M6
20/0.5

M9
30/2
M11
15/1

VSS

16

Current Mirror Biasing

Example 2

VDD
M2
5/0.5

M6
25/0.5

M10
10/0.5

M4
10/1
VI

M1
40/1
M3
10/0.5

M8
25/1
M5
20/0.5
M7
15/0.5

M9
5/0.5

17

MOSFET Small-Signal Operation

iD =
=

kn W
2 L

(VGS + vgs Vt)2 =

kn W
2 L

W
kn W 2
k W 2
Vov + kn Vov vgs + n vgs
2 L
L
2 L
Assume vgs

iD

VGS
vgs

(Vov + vgs)2

2Vov , then

iD ID + kn

VDS

Vov vgs

L
= ID + gmvgs
= ID + id
W

gm = kn Vov
L

18

Small-Signal Model

NMOS

gm = kn Vov = 2kn ID
L
L
ro =

VA
ID

nID

is
G

D
vgs

gm vgs

S
model

ro

ro
1
gm

is

S
T model

19

Small-Signal Model

PMOS

gm = kp Vov = 2kp ID
L
L
ro =

|VA|
ID

|p|ID

1
gm

is
ro

G
is

vsg

gm vsg

ro
D

model

D
T model

20

MOS Node Resistances

AC, ro =

RD

Rgate =

Rgate
RS

Rdrain

Rdrain =

RG
RS

RD
RG

Rsource

Rsource =

1
gm

21

Common-Source Amplier

Discrete

VDD
RG1
Rx

RD

Ro
vo

VG
RL

vi
Ri

RG2

In

RS

VSS
ID = I n ,

VG = VSS +

RG2
RG1 + RG2

(VDD + VSS)

22

Common-Source Amplier

Rx

AC equivalent, ro =

vo

vg
RD

vi

Ro

RG

RS

Ri

Ri = RG

Rgate = RG1

Ro = RD
vg
vi

RL

RG2

Rgate

Rdrain

Ri
Rx + Ri

vo

RD RL
=
1
vg
+ RS
gm

23

Common-Drain Amplier

Discrete

VDD
RG1

Rx

VG

vo

vi
Ri

RG2

In
Ro

RL

VSS
ID = I n ,

VG = VSS +

RG2
RG1 + RG2

(VDD + VSS)

24

Common-Drain Amplier
Rx

AC equivalent, ro =

vg

vi

Ro

RG

vo

Ri
RL

Ri = RG

Rgate = RG1

RG2

Rgate

Ro = Rsource
vg
vi

Ri
Rx + Ri

vo
vg

RL
1
gm

+ RL

25

Common-Gate Amplier

Discrete

VDD
RG1

RD

Ro
vo

VG
RL
RG2
Rx

In
VSS
ID = I n ,

VG = VSS +

vi

Ri
RG2
RG1 + RG2

(VDD + VSS)

26

Common-Gate Amplier

AC equivalent, ro =

vo

RG
RD

RL

Ro

vs
vi

Rx
Ri
Ri = Rsource
Ro = RD
vs
vi

Rdrain

Ri
Rx + Ri

vo
vs

RD

RL

Rsource

27

MOSFET Ampliers - Summary

RD

RD
vo

vo

vi

1
gm

+ RS

RS

RG

RS

RD

vo

vi

vi

vi

vo

AC, ro =

vo
vi

RD
Rsource

vo
vi

RS
1
gm

+ RS

28

MOS Node Resistances

AC, ro nite

RD
Rgate

Rgate =

RS

Rdrain

RG

Rdrain = gmroRS + ro + RS
RS

RD

RG

Rsource

Rsource =

ro 1 +

gm

RD

ro

29

Common-Source Amplier

Integrated

VDD
M3

M2

VD3
R

kp W

ID3 =

vI

M1

vO

L 3

(VDD VD3 |Vtp|) =

VD3
R

ID2

L
= W 2 ,

ID3

L 3

ID1 = ID2

30

Common-Source Amplier

ro2

AC equivalent

vo
vi

ro1

vo
vi

M1

ro2
1

gm1
Ri =

Ro
Ro = ro1

ro2

Ri

31

Common-Drain Amplier

Integrated

VDD
R

vI

M1
vO

VD3
M3
kn W

ID3 =

M2

L 3

(VD3 Vtn) =

VDD VD3
R

ID2

L
= W 2 ,

ID3

L 3

ID1 = ID2

32

Common-Drain Amplier

AC Equivalent

vo

vi

M1

Ro

vi

ro1
1
gm1

vo

Ri

ro2

+ (ro1

ro2)

Ri =

ro2
Ro =

1
gm1

ro1

ro2

33

Two-Port Modeling of Ampliers

Twoport

Vi

Network

Vo

vi

Ri

vi

Gm vi

vo
vi

Rn

vo

= GmRn

34

Two-Port Modeling of Ampliers

vi

Ri

vi

Gm =

Gm vi

Gm & Rn

Rn

vo

isc

isc
vi vo=0

io
Ri

vi

Gm vi

Rn =

Rn

vo

vo
io vi=0
35

Two-Port Modeling of Ampliers

#1

v1

#2

v2

v3

#3

Multistage

vN1

vo

#N

vi
Ri

vi

ii

#1

#2

#3

#N

Ro
#1

vo

#2

v1 v 2
vo
=

vi
vi v 1
vN 1

#3

#N

Ri =

vi
ii

Ro =

io

vo

vo
io

36

Two-Port Modeling of Ampliers

#1

v1

v2

#2

v3

#3

Multistage

vN1

vo

#N

vi

#1
vi

#2

#3

#N

#2

#3

#N

isc1

#1
Rn1

Gm1 =

isc1

v1

vi

vi

= Gm1Rn1

37

Two-Port Modeling of Ampliers

#1

v1

#2

v2

v3

#3

Multistage

vN1

vo

#N

vi

#2
v1

#3

#N

#3

#N

isc2

#2
Rn2

Gm2 =

isc2

v2

v1

v1

= Gm2Rn2

38

Two-Port Modeling of Ampliers

#1

v1

v2

#2

v3

#3

Multistage

vN1

vo

#N

vi

#N
vN1

iscN

#N
RnN

GmN =

iscN

vo

vN 1

vN 1

= GmNRnN

39

Common-Gate Amplier

Integrated

VDD
M3

M2

VD3
R

vO
VB

M1
vI

kp W

ID3 =

L 3

(VDD VD3 |Vtp|) =

VD3
R

ID2

L
= W 2 ,

ID3

L 3

ID1 = ID2

40

Common-Gate Amplier

AC Equivalent

Ri =

ro1 1 +

gm1

ro2

ro1

ro2
Gm = gm1 +

vo
M1

vi

Rn = ro1

Ri

vo
vi

1
ro1

ro2

= GmRn

41

Common-Source Amplier - SD

Integrated

VDD
M3

M2
vO

VD3
Rx

vI

M1
Rs

kp W

ID3 =

L 3

(VDD VD3 |Vtp|) =

VD3
Rx

ID2

L
= W 2 ,

ID3

L 3

ID1 = ID2

42

Common-Source Amplier - SD

AC equivalent

Ri =

ro2
vo
vi

Gm =

gm1
1 + gm1Rs + (Rs/ro1)

M1
Rn = ro2

Ri

(Rs + ro1 + gm1Rsro1)

Rs
vo
vi

= GmRn

43

MOSFET Ampliers- Summary

AC, ro nite

RD
vo

vo

vi
RS

vi

vo
vi

RD ro
1
gm

vo
vi

RS
1
gm

ro

+ (RS

ro)

44

MOSFET Ampliers - Summary

AC, ro nite

RD
RD

vo

vo
vi

vi

RG

RS
gm

Gm =

1 + gmRS +
Rn = RD
vo
vi

RS
ro

(gmroRS + ro + RS )

= GmRn

Gm = gm +
Rn = RD
vo
vi

1
ro

ro

= GmRn

45