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Vlsi Mtech Jntu Kakinada Syllabus

The document provides the course structure for the M.Tech program in Electronics and Communication Engineering at Jawaharlal Nehru Technological University in Kakinada, India. It lists 4 core subjects, 2 elective subjects, and 1 laboratory subject for the first semester. It also provides unit details and textbook references for the subject "Digital System Design".

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0% found this document useful (0 votes)
10K views11 pages

Vlsi Mtech Jntu Kakinada Syllabus

The document provides the course structure for the M.Tech program in Electronics and Communication Engineering at Jawaharlal Nehru Technological University in Kakinada, India. It lists 4 core subjects, 2 elective subjects, and 1 laboratory subject for the first semester. It also provides unit details and textbook references for the subject "Digital System Design".

Uploaded by

aditya414
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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w.e.

f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


KAKINADA 533 003

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


M. Tech- I Semester

Specialization: VLSID/VLSISD

COURSE STRUCTURE

Code Name of the Subject L P C INT EXT TOTAL


Core
1. Digital System Design 4 - 8 40 60 100
2. VLSI Technology & Design 4 - 8 40 60 100
3. Analog & Digital IC Design 4 - 8 40 60 100
4. Embedded Systems Concepts 4 - 8 40 60 100
Elective I
1. VHDL Modeling of Digital 4 - 8 40 60 100
Systems
2. Digital Data Communications
Elective II
1.Electronic Design Automation 4 - 8 40 60 100
Tools
2.Embedded System Design
Laboratory
1.HDL Programming Laboratory - 4 4 40 60 100
w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

DIGITAL SYSTEM DESIGN

UNIT – I
DESIGN OF DIGITAL SYSTEMS: ASM charts, Hardware description language and control
sequence method, Reduction of state tables, state assignments.

UNIT – II
SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits, design of sequential circuits
using ROMs and PLAs, sequential circuit design using CPLD, FPGAs.

UNIT – III
FAULT MODELING: Fault classes and models – Stuck at faults, bridging faults, transition and
intermittent faults. TEST GENERATION: Fault diagnosis of Combinational circuits by
conventional methods – Path
Sensitization technique, Boolean difference method, Kohavi algorithm.

UNIT – IV
TEST PATTERN GENERATION: D – algorithm, PODEM, Random testing, transition count
testing, Signature analysis and testing for bridging faults.

UNIT – V
FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault detection
experiment. Machine identification, Design of fault detection experiment.

UNIT – VI
PROGRAMMING LOGIC ARRAYS: Design using PLA’s, PLA minimization and PLA
folding.

UNIT – VII
PLA TESTING: Fault models, Test generation and Testable PLA design.

UNIT – VIII
ASYNCHRONOUS SEQUENTIAL MACHINE: fundamental mode model, flow table, state
reduction, minimal closed covers, races, cycles and hazards.
TEXT BOOKS:

1. Z. Kohavi – “Switching & finite Automata Theory” (TMH)


2. N. N. Biswas – “Logic Design Theory” (PHI)
3. Nolman Balabanian, Bradley Calson – “Digital Logic Design Principles” – Wily Student
Edition
2004.

REFRENCE BOOKS:

1. M. Abramovici, M. A. Breues, A. D. Friedman – “Digital System Testing and Testable


Design”,
Jaico Publications
2. Charles H. Roth Jr. – “Fundamentals of Logic Design”.
3. Frederick. J. Hill & Peterson – “Computer Aided Logic Des
ign” – Wiley 4th
Edition. 4

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

VLSI TECHNOLOGY & DESIGN

UNIT – I
REVIEW OF MICROELECTRONICS AND INTRODUCTION TO MOS TECHNOLOGIES:
(MOS, CMOS, Bi CMOS) Technology trends and projections.

UNIT – II
BASIC ELECTRICAL PROPERTIES OF MOS, CMOS & BICOMS CIRCUITS: Ids-Vds
relationships, Threshold voltage Vt, Gm, Gds and Wo, Pass Transistor, MOS,CMOS & Bi
CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model,Latch-up in CMOS circuits.

UNIT – III
LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias , Scalable Design
rules ,Layout Design tools.

UNIT – IV
LOGIC GATES & LAYOUTS: Static complementary gates, switch logic, Alternative gate
circuits, low power gates, Resistive and Inductive interconnect delays.
UNIT – V
COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, interconnect
design, power optimization, Switch logic networks, Gate and Network testing.

UNIT – VI
SEQUENTIAL SYSTEMS: Memory cells and Arrays, clocking disciplines, Design ,power
optimization, Design validation and testing.

UNIT – VII
FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods, off-chip
connections, High-level synthesis, Architecture for low power, SOCs and Embedded CPUs,
Architecture testing.

UNIT – VIII
INTRODUCTION TO CAD SYSTEMS (ALGORITHMS) AND CHIP DESIGN: Layout
Synthesis and Analysis, Scheduling and printing; Hardware/Software Co-design, chip design
methodologies- A simpleDesign example-

TEXT BOOKS:
1. Essentials of VLSI Circuits and Systems, K. Eshraghian et . al( 3 authors) PHI of India
Ltd.,2005
2. Modern VLSI Design, 3rd Edition, Wayne Wolf ,Pearson Education, fifth Indian
Reprint, 2005.

REFERENCES:
1. Principals of CMOS Design – N.H.E Weste, K.Eshraghian, Adison Wesley, 2nd
Edition.
2. Introduction to VLSI Design – Fabricius, MGH International Edition, 1990.
3. CMOS Circuit Design, Layout and Simulation – Baker, Li Boyce, PHI, 2004. 3

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

ANALOG AND DIGITAL IC DESIGN

UNIT-I

OPERATIONAL AMPLIFIERS: General considerations one – state op-amps, two stage op-amps-gains
boosting stage- comparison I/P range limitations slew rate. CURRENT MIRRORS AND SINGLE
STAGE AMPLIFIERS: simple COMS, 3JT current mirror,, Cascode Wilson Wilder current mirrors.
Common Source amplifier source follower, common gate amplifier
NOISE: Types of Noise – Thermal Noise-flicker noise- Noise in opamps- Noise in common source stage
noise band width.

UNIT-II

PHASED LOCKED LOOP DESIGN: PLL concepts- The phase locked loop in the locked condition
Integrated circuit PLLs – phase Detector- Voltage controlled oscillator c ase study: Analysis of the 560
B Monolithic PLL.

SWITHCHED CAPACITORS CIRCUITS: Basic Building blocks op-amps capacitors switches –


non-over lapping clocks-Basic operations and analysis-resistor equivalence of la switched
capacitor- parasitic sensitive integrator parasitic insensitive integrators signal flow graph
analysis-First order filters- switch sharing fully differential filters – charged injections-switched
capacitor gain circuits parallel resistor –capacitor circuit – preset table gain circuit – other
switched capacitor circuits – full wave rectifier – peak detector sinusoidal oscillator.

UNIT-III

LOGIC FAMILIES & CHARACTURISTICS : COMS, TTL, ECL, logic families COMS / TTL,
interfacing comparison of logic families.
COMBINATIONAL LOGIC DESIGN USING VHDL: VHDL modeling for decoders, encoders,
multiplexers, comparison, adders and subtractors .
SEQUENCIAL IC DESIGN USING VHD: VHDL modeling for larches, flip flaps, counters,
shift registers, FSMs.

UNIT-IV
DIGITAL INTEGRADED SYSTEM BUILDING BLOCKS: Multiplexers and decoders – barrel
shifters counters digital single bit adder
MEMORIES: ROM: Internal structure 2D decoding commercial type timing and applications
CPLD: XC 9500 series family CPLD architecture – CLB internal architecture, I/O block internal
structure .
FPGA: Conceptual of view of FPGA – classification based on CLB internal architecture I/O
block architecture.

UNIT-V
COMPORATORS: Using an op-amp for a comparator-charge injection errors- latched
comparator
NYQUIST RATE D/A CONVERTERS: Decoder based converter resistor storing converters
folded resister string converter – Binary scale converters – Binary weighted resistor converters –
Reduced resistance ratio ladders – R-2R based converters – Thermometer code current mode
D/A converters.
NYQUIST RATE A/D CONVERTERS: Integrating converters – successive approximation
converters. DAC based successive approximation – flash converters time interleaved A/D
converters.
REFERENCES:

1. Analog Integrated circuit Design by David A Johns, Ken Martin, John Wiley & Sons.
2. Analysis and design of Analog Integrated Circuits, by Gray, Hurst Lewis, Meyer. John
Wiley & Sons.
3. Design of Analog CMOS Integrated Circuits, Behzad Razavi, TMH
4. Digital Integrated Circuit Design by Ken Martin, Oxford University 2000
5. Digital Design Principles & Practices” by John F Wakerly, Pearson Education & Xilinx
Design Series, 3rd Ed.(2002)

SUGGESTING READOMG

1. Ken Martin, Digital Integrated Circuit Design Oxford University,2000.


2. John F Wakerly, “Digital Design Principles & Practices”, Pearson Education &
Xilinx Design Series, 3rd Ed.(2002)
3. Samir Palnitkar, “Verylog HDL-A Guide to Digital Design and Synthesis”, Prentice
Hall India, (2002)
4. Douglas J Smith, “HDL Chip Design, a practical Guide for Designing, Synthesizing
and simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications,
(1999).

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

EMBEDDED SYSTEMS CONCEPTS

UNIT I: AN INTRODUCTION TO EMBEDDED SYSTEMS


An Embedded system, processor in the system, other hardware units, software embedded into a
system,exemplary embedded systems, embedded system – on – chip (SOC) and in VLSI circuit.
Processor and memory organization – Structural Units in a Processor, Processor selection for an
embedded system, memory devices, memory selection for an embedded systems, allocation of
memory to program cache and memory management links, segments and blocks and memory
map of a system, DMA, interfacing processors, memories and Input Output Devices.

UNIT II: DEVICES AND BUSES FOR DEVICE NETWORKS


I/O devices, timer and counting devices, serial communication using the “I2 C” CAN, profibus
foundation
field bus. and advanced I/O buses between the network multiple devices, host systems or
computer parallel
communication between the networked I/O multiple devices using the ISA, PCI, PCI-X and
advanced buses.
UNIT III: DEVICE DRIVERS AND INTERRUPTS SERVICING MECHANISM
Device drivers, parallel port and serial port device drivers in a system, device drivers for internal
programmable timing devices, interrupt servicing mechanism

UNIT IV: PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C, C++,


VC++ AND JAVA
Interprocess communication and synchronization of processes, task and threads, multiple
processes in an application, problem of sharing data by multiple tasks and routines, interprocess
communication.

UNIT V: HARDWARE – software co-design in an embedded system, embedded system project


management, embedded system design and co-design issues in system development process,
design cycle in the development phase for an embedded system, use of target systems, use of
software tools for development of an embedded system, use of scopes and logic analysis for
system, hardware tests. Issues in embedded system design.

TEXT BOOK:
1. Embedded systems: Architecture, programming and design by Rajkamal, TMH.

REFERENCE:
1. Embedded system design by Arnold S Burger, CMP
2. An embedded software primer by David Simon, PEA
3. Embedded systems design:Real world design be Steve Heath; Butterworth Heinenann,
Newton mass
USA 2002
4. Data communication by Hayt.

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

VHDL MODELLING OF DIGITAL SYSTEMS (ELECTIVE I)

UNIT I INTRODUCTION :
An Overview Of Design Procedures Used For System Design Using CAD Tools. Design Entry.
Synthesis, Simulation, Optimization, Place And Route. Design Verification Tools. Examples
Using Commercial PC Based On VHDL Elements Of VHDL Top Down Design With VHDL
Subprograms. Controller Description VHDL Operators.

UNIT II BASIC CONCEPT IN VHDL: Characterizing Hardware Languages, Objects And


Classes, Signal Assignments, Concurrent And Sequential Assignments. Structural Specification
Of Hardware: Parts Library Wiring Of Primitives, Wiring Interactive
Networks, Modeling A Test Bench Binding Alternative Top Down Wiring.
UNIT III DESIGN ORGANIZATIN AND PARAMETERIZATION:
Definition And Usage If Subprograms, Packaging Parts And Utilities, Design Parametrization,
Design Configuration, Design Libraries, Utilities For High –Level Descriptions-Type
Declaration And Usage, VHDL Operators, Subprogram Parameter Types And Overloading,
Other Types And Type Related Issues, Predefined Attributes, User Defined Attributes, Packing
Basic Utilities.

UNIT IV DATA FLOW DESCRIPTION IN VHDL


Multiplexing And Data Selection, State Machine Description, Open Collector Gates, Three State
Bussing AGeneral Data Flow Circuit, Updating Basic Utilities. Behavioral Description Of
Hardware: Process Statement Assection Statements, Sequential Wait Statements Formatted
ASCII I/O Operators, MSI-Based Design.

UNIT V CPU MODELLING FOR DESCRIPTION IN VHDL:


Parwan CPU, Behavioural Description Of Parawan, Bussing Structure, Data Flow Description
Test Bench For The Parwan CPU. A More Realistic Parwan. Interface Design And Modeling.
VHDL As A Modelling Language.

TEXT BOOKS:

1. Z.NAWABI : VHDL Analysis And Modelling Of Digital Systems. (2/E), Mcgraw Hill,
(1998)
REFERENCE:
1. PERRY : VHDL, (3/E) Mcgraw Hill 10

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

DIGITAL DATA COMMUNICATIONS ( Elective –I )

UNIT I DIGITAL MODULATION TECHNIQUES


FSK , MSK , BPSK , QPSK , 8-PSK , 16-PSK , 8- QAM , 16- QAM , Band width efficiency
carrier recovery DPSK , clock recovery , Probability of error and bit error rate.

UNIT II
Data Communications ; Serial , Parallel configuration , Topology , Transmission modes , codes ,
Error Control Synchronization, LCU.

UNIT III
Serial and Parallel Interfaces , Telephone Networks and Circuits , Data modems.
UNIT IV
Data Communication Protocols , Character and block Mode ,Asynchronous and Synchronous
Protocols, public Data Networks , ISDN.

UNIT V
LOCAL AREA NETWORKS: token ring, Ethernet, Traditional, Fast and GIGA bit Ethernet,
FDDI

UNIT VI
DIGITAL MULTIPLEXING : TDM , T1 carrier , CCITT , CODECS, COMBO CHIPS , North
American Hierarchy , Line Encoding , T-carrier , Frame Synchronization Inter Leaving
Statistical TDM FDM , Hierarchy ,Wave Division Multiplexing .

UNIT VII
WIRELESS LANS
IEEE 802.11 Architecture Layers, Addressing, Blue Tooth Architecture Layers, l2 Cap, Other
Upper Layers .

UNIT VIII
MULTI MEDIA
Digitalizing Video and Audio Compression Streaming Stored and Live Video and Audio , Real
Time Interactive Video and Audio , VOIP

TEXT BOOKS
1. Electronic communication systems, fundamentals through advanced - W. TOMASI, Pearson
4th Edition.
2. Data communication and networking - B.A. Forouzen

w.e.f 2009-2010

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA


DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

ELECTRONIC DESIGN AUTOMATION TOOLS


(Elective –II )
UNIT I
IMPORTANT CONCEPTS IN VERILOG:
Basics Of Verilg Language, Operators, Hierarchy,Procedures And Asignments,Timing Controls
And Delay.
Tasks And Functions Control Statements, Logic-Gate Modeling, Modeling Delay, Altering
Parameters,
Other Verilog Features.
UNIT II
SYNTHESIS AND SIMULATION USING HDLS:
Verilog And Logic Synthesis. VHDL And Logic Synthesis, Memory Synthesis,FSM
Synthesis,Memory
Synthesis, Performance-Driven Synthesis. Simulation-Types Of Simulation, Logic Systems
Working Of
Logic Simulation,Cell Models, Delay Models State Timing Analysis,Formal Verification,
Switch-Level
Simulation Transistor-Level Simulation. CAD Tools For Synthesis And Simulation Modelism
And Leonardo
Spectrum(Exemplar).

UNIT III
TOOLS FOR CIRCUIT DESIGN AND SIMULATION USING PSPICE:
Pspice Models For Transistors, A/D & D/A Sample And Hold Circuits Etc, And Digital System
Building
Blocks, Design And Analysis Of Analog And Digital Circuits Using PSPICE.

UNIT IV
AN OVER VIEW OF MIXED SIGNAL VLSI DESIGN:
Fundamentals Of Analog And Digitla Simulation,Mixed Signal Simulator Configurations,
Understanding
Modeling, Integration To CAE Environmets, Analyses Of Analog Circuits Eg.A/D, D/A
Converters, Up And
Down Converters, Companders Etc.

UNIT V
TOOLS FOR PCB DESIGN AND LAYOUT:
An Overview Of High Speed PCB Design, Design Entry, Simulation And Layout Tools For
PCB.
Introduction To Orcad PCB Design Tools.

TEXTBOOKS
1. J.Bhaskar, A Verilog Primer, BSP, 2003.
2. J.Bhaskar, A Verilog HDL Synthesis BSP, 2003
3. M.H.RASHID:SPICE FOR Circuits And Electronics Using PSPICE (2/E)(1992) Prentice
Hall.

REFERENCES
1. ORCAD: Technical Reference Manual ,Orcad, USA.
2. SABER: Technical Reference Manual, Analogy Nic, USA.
3. M.J.S.SMITH :Aplication-Specific Integrated Circuits(1997). Addison Wesley
4. J.Bhaskar, A VHDL Synthesis Primer, BSP, 2003.
w.e.f 2009-2010
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
M. Tech- I Semester

HDL PROGRAMMING LABORATORY

1. Digital Circuits Description using Verilog and VHDL

2. Verification of the Functionality of Designed circuits using function Simulator.

3. Timing simulation for critical path time calculation.

4. Synthesis of Digital circuits

5. Place and Route techniques for major FPGA vendors such as Xilinx, Altera and Actel etc.

6. Implementation of Designed Digital Circuits using FPGA and CPLD devices.

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