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Lab 6

This document describes an experiment to implement 2x1 and 4x1 multiplexers (MUX) using data flow modeling in Verilog. A MUX is a logic circuit that selects one of several input lines based on select lines and outputs the selected input. The experiment implements a 2x1 MUX with inputs I0 and I1, select line S, and output Y. It also implements a 4x1 MUX with inputs I0-I3, select lines S0 and S1, and output Y. The boolean functions and logic diagrams for each MUX are provided. The Verilog code for the 4x1 MUX implementation is also included.

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39 views3 pages

Lab 6

This document describes an experiment to implement 2x1 and 4x1 multiplexers (MUX) using data flow modeling in Verilog. A MUX is a logic circuit that selects one of several input lines based on select lines and outputs the selected input. The experiment implements a 2x1 MUX with inputs I0 and I1, select line S, and output Y. It also implements a 4x1 MUX with inputs I0-I3, select lines S0 and S1, and output Y. The boolean functions and logic diagrams for each MUX are provided. The Verilog code for the 4x1 MUX implementation is also included.

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USMAN INSTITUTE OF TECHNOLOGY

HAMDARD UNIVERSITY
DEPARTMENT OF ELECTRICAL ENGINEERING

VLSI DESIGN (EE-411)


SPRING-2014
Engr. Zohaib Jawaid
Engr. Kashif Ali Arshad
Engr. S. Aimen Naseem
Engr. Sameer Ahmad

EXPERIMENT 6#: Implementation of 2x1 MUX and 4x1 MUX Using Data Flow Modeling

Name of Student: _____________________________________________________________

Roll No.: _________________________________Group:_____________________________

Date of Experiment

: _____________________________________________

Report Submitted on

: _____________________________________________

Marks Obtained

: ______________________________________________

Remarks if any

: ______________________________________________

Signature

: _____________________________________________

OBJECT: Implementation of 2x1 MUX and 4x1 MUX Using Data Flow Modeling.
DESCRIPTION:
In this lab we will implement different types of multiplexers using data flow modeling. Prior to
the explanation of the code, a multiplexer is a logic circuit that has several inputs and one output
and based on the select inputs any one of the input will be selected as the output.
The number of inputs is generally a multiple of 2 (2, 4, 8, 16, etc.), the number of outputs is
either 1 or relatively small multiple of 2, and the number of control signals is related to the
combined number of inputs and outputs. For example, a 2-input, 1-output MUX requires only 1
control signal to select the input, while a 16-input, 4-output MUX requires 4 control signals to
select the input and 2 to select the output.
Multiplexer, simply called MUX, is a data selector and is capable of selecting one of many
input lines (usually 2n) and display its input status on the only output line available.
A MUX has
1.
Select lines
2.
Data input lines
3.
Output line.
Block diagram of 2x1 MUX
I0
2X1 MUX

data i/p lines

output

I1

I0, I1 are inputs of MUX S is select line Y is


output
The function table of 2x1 MUX is
Select line
S
0
1

select line

The Boolean function for 2x1 MUX is Y = I1 s + I0 s


Logic Diagram of 2x1 MUX is
I1

I0

I1 s
I1 s + I0 s' = Y
To LED

s'
I0 s'

o/p
Y
Io
I1

Block diagram of 4x1 MUX


I0
data i/p lines

I1
I2
I3

4X1 MUX

Y
output

S1

S0

select lines

I0, I1,I2 and I3 are input S1 and S0 are select


inputs, Y is output
The Boolean function for 4x1 MUX is
Y = I0 S1 S0+ S1 S0 I1+ S1 S0 I2+ S1 S0I3
Logic Diagram of 4x1 MUX
Consider the verilog code for the 4x1 MUX-:

The function table of 4x1 MUX is


Select
o/p
lines
S1
S0
Y
0
0
Io
0
1
I1
1
0
I2
1
1
I3

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