8086 interrupts

KARTHIK. S
27/02/2014
BASIC TYPES
INTERRUPTS
maskable non-maskable
immediate response by microprocessor microprocessor can ignore
INTR
Groups
The 80x86 chips allow up to 256 vectored
interrupts.
VECTORED VECTORED
NON-VECTORED NON-VECTORED
INTERRUPT VECTOR TABLE
This is a 1K table containing 256 4-
byte entries
Each entry in this table contains a
segmented address that points at the
interrupt service routine in memory.
The interrupt vector table is located in the first 1024 bytes of
memory at addresses 000000H0003FFH.
Type 0
The divide error whenever the result from a division overflows or an
attempt is made to divide by zero.
Type 1
Single-step or trap occurs after execution of each instruction if the trap
(TF) flag bit is set.
upon accepting this interrupt, TF bit is cleared
so the interrupt service procedure executes at
full speed
Type 2
The non-maskable interrupt occurs when a logic 1 is placed on the NMI input pin
to the microprocessor.
non-maskableit cannot be disabled
Type 3
A special one-byte instruction (INT 3) that uses this vector to access its interrupt-
service procedure.
often used to store a breakpoint in a program
for debugging
Type4
Overflow is a special vector used with the INTO instruction. The INTO
instruction interrupts the program if an overflow condition exists.
as reflected by the overflow flag (OF)
Type 5
The BOUND instruction compares a register with boundaries stored in the memory. If the
contents of the register are out of bounds, a type 5 interrupt ensues
The next 27 interrupt types, from 5 to 31 are reserved by Intel
for use in future microprocessors.
The upper 224 interrupt types, from 32 to 255, are available
to use for hardware and software interrupts
The next 27 interrupt types, from 5 to 31 are reserved by Intel
for use in future microprocessors.
The upper 224 interrupt types, from 32 to 255, are available
to use for hardware and software interrupts
What happens? What happens?
HOW?
The CPU pushes the flags register onto the stack
The CPU pushes a far return address (segment :
offset) onto the stack, segment value first.
The CPU determines interrupt number and fetches
the four byte interrupt vector from address
0:vector*4.
The CPU transfers control to the routine
The CPU pushes the flags register onto the stack
The CPU pushes a far return address (segment :
offset) onto the stack, segment value first.
The CPU determines interrupt number and fetches
the four byte interrupt vector from address
0:vector*4.
The CPU transfers control to the routine