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Low Power Vlsi Syallbus

This document outlines the units covered in a course on Low Power VLSI Design. Unit 1 introduces the need for low power chips and sources of power dissipation. Unit 2 discusses how device and technology impact dynamic dissipation and transistor sizing. Unit 3 covers simulation tools for power analysis like capacitive power estimation and probabilistic techniques. Unit 4 discusses circuit-level techniques like flip-flop design and logic-level optimizations. Unit 5 addresses power management techniques and low power architectures for memory and arithmetic components.

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Mahesh Kumar
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42 views1 page

Low Power Vlsi Syallbus

This document outlines the units covered in a course on Low Power VLSI Design. Unit 1 introduces the need for low power chips and sources of power dissipation. Unit 2 discusses how device and technology impact dynamic dissipation and transistor sizing. Unit 3 covers simulation tools for power analysis like capacitive power estimation and probabilistic techniques. Unit 4 discusses circuit-level techniques like flip-flop design and logic-level optimizations. Unit 5 addresses power management techniques and low power architectures for memory and arithmetic components.

Uploaded by

Mahesh Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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(DE7)

Low Power VLSI Design


Unit-1: Introduction
Need for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits.
Emerging Low power approaches. h!sics of power dissipation in "#$S de%ices.
Unit-2: Device & Technology Im!ct on Low Power
D!namic dissipation in "#$S, &ransistor si'ing ( gate o)ide thic*ness, Impact of technolog!
Scaling, &echnolog! ( De%ice inno%ation.
Unit-": Simul!tion Power !n!lysis+
SI"E circuit simulators, gate le%el logic simulation, capaciti%e power estimation, static state
power, gate le%el capacitance estimation, architecture le%el anal!sis, data correlation anal!sis in
DS s!stems. #onte "arlo simulation. ,andom logic signals, pro-a-ilit! ( fre.uenc!,
pro-a-ilistic power anal!sis techni.ues, signal entrop!.
Unit-#: Low Power Design
Circuit level: ower consumption in circuits. /lip /lops ( Latches design, high capacitance
nodes, low power digital cells li-rar!
Logic level: 0ate reorgani'ation, signal gating, logic encoding, state machine encoding, pre1
computation logic
Unit-$: Low ower %rchitecture & Systems:
ower ( performance management, switching acti%it! reduction, parallel architecture with
%oltage reduction, flow graph transformation, low power arithmetic components, low power
memor! design. ower dissipation in cloc* distri-ution, single dri%er Vs distri-uted -uffers, 2ero
s*ew Vs tolera-le s*ew, chip and pac*age co1design of cloc* networ*, Introduction of design
flow, algorithmic le%el anal!sis and optimi'ation, 3rchitectural le%el estimation and
S!nthesis.
T&'T()&*&)&+,& -../S:
4. 0ar! 5ap, ractical Low ower Digital VLSI Design 4667.
7. 8aushi* ,o!, Sharat rasad, Low ower "#$S VLSI "ircuit Design, 7999

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