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State Cad Tutorial

This document provides instructions for using StateCAD software to generate VHDL code from state diagrams. It describes how to create a new state machine project, design a state diagram with 4 states and transitions between them controlled by an EN signal, set output conditions for each state, optimize the design for an FPGA target, and generate VHDL code along with an automatic test bench.

Uploaded by

Huzur Ahmed
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
69 views

State Cad Tutorial

This document provides instructions for using StateCAD software to generate VHDL code from state diagrams. It describes how to create a new state machine project, design a state diagram with 4 states and transitions between them controlled by an EN signal, set output conditions for each state, optimize the design for an FPGA target, and generate VHDL code along with an automatic test bench.

Uploaded by

Huzur Ahmed
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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State Cad Tutorial J imDuckworth

Using StateCAD to generate VHDL from State Diagrams



Select Project => New Source and select State Diagram.

StateCAD starts

Select File => Design Wizard or click on the Draw State Machine button



Click on Next



To make our SM1 state machine, select 4 states

Click on Next

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State Cad Tutorial J imDuckworth


Select Asynchronous reset then Next



The Optimization Wizard may open at this point (click cancel we will run this later)


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Now we need to add the transitions from state to state.

Click on the transition from State0 to State1 and add EN=1 as shown:



Click on OK


Repeat for the other transitions:

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Now we need to set the output conditions:

Double-click on State0 and add C <= 0; as shown



and repeat for the other states

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You can go straight to Generate HDL (Options =>Compile), but first click on the
Optimize button. Click Next. Select FPGA in Select Target Device Window

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Click on Next to end the Optimize wizard.

Click on the Generate HDL button:



Click on Close and the HDL code generated is shown:


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You can change the generated VHDL by Options => Configuration



Click OK or Cancel.

Click on the State Bench button then click on Automatic Test Bench





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Click Begin


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