2012EEE2188 DSP Experiment 5
2012EEE2188 DSP Experiment 5
A. Parallel MAC - Asymmetric N .set 4;h M .set 4;x .mmregs .def start start BCLR C54CM BCLR AR0LC ;Linear Mode AMOV #01000h,XAR0 ;Starting Address for Input X AMOV #01000h+1,XAR2 ;XXXXXXXX BCLR AR1LC ;Linear Mode AMOV #010020h,XAR1 ;Starting Address for Output BSET CDPLC ;Circular Addressing BSET SATD ;To Saturate Accumulator BSET FRCT ;To shift Accumulator left by one bit AMOV #000100h,XCDP ;Starting Address for coefficient H MOV #0h,BSAC ;Offset for circular Addressing of CDP MOV #N,BKC ;Size of Block for Circular Addressing MOV #(M+N-1)/2,BRC0 ;Initializing for local block repeat BR0+1 times MOV #N+1,T0 ;Offset to move pointer of AR0 back. RPTBLOCAL LOOP MOV #0,AC0 MOV #0,AC1 RPT #N-2 MAC *AR0-,*CDP+,AC0 :: MAC *AR2-,*CDP+,AC1 MAC *(AR0+T0),*CDP+,AC0 :: MAC *(AR2+T0),*CDP+,AC1 MOV HI(AC0),*AR1+ ;Storing Output LOOP MOV HI(AC1),*AR1+ ;Storing Output IDLE B. Using Parallel MAC - Symmetric N M .set 4 ;no filter coefficients .set 4 ;size of input .mmregs .def start
; ; ;
AMOV #010000H,XAR0 ;Input Start Addr BCLR AR2LC ; Set Linear Mode AMOV #01000AH,XAR2 ; Input Start Addr BSET CDPLC AMOV #000100H,XCDP BCLR AR1LC ; Set Linear Mode AMOV #010020h,XAR1 ; Output Start Addr BCLR AR3LC ; Set Linear Mode AMOV #01002Ah,XAR3 BCLR AR3LC ; Set Linear Mode AMOV #01002Ah,XAR4 ; Output Start Addr
BSET CDPLC ; Circular Adressing BSET SATD ; Saturate Accumalator BSET FRCT ; Left Shift Acc by 1 bit ; AMOV #000100h,XCDP ;Statr Addr of Coefficients MOV #0h,BSAC ;Offset for Circular addressing of CDP MOV #N,BKC ;Size of Block for Circular Address ;MOV #0h,BSAC ;MOV #N,BKC ; MOV #0h,AC0 ; MOV #0h,AC1 ; MOV #(M/2)-1,BRC0 ; Initialization of Local Block repeat ; MOV #M-1,BRC2 MOV #N,T0 ;Offset to move pointer Of AR0 back RPTBLOCAL LOOP MPYM *AR0-,*CDP,AC0 ; MPYM *AR2-,*CDP+,AC1 ; ;MOV #N-1,T1 ;RPTBLOCAL LOOP ;MOV #0h,AC0 ;Repeats BRC0+1 times RPT #(N-3) MAC *AR0-,*CDP+,AC0 :: MAC *AR2-,*CDP+,AC1 ; MAC *(AR0+T0),*CDP+,AC0 :: MAC *(AR2+T0),*CDP+,AC1 ; LOOP MOV HI(AC0),*AR1+ :: MOV HI(AC1),*AR4+ ;Store at Oupput loc. IDLE
start
BCLR C54CM BCLR AR0LC ;Linear Mode AMOV #01000h,XAR0 ;Starting Address for Input X AMOV #01000h+1,XAR2 BCLR AR1LC ;Linear Mode AMOV #010020h,XAR1 ;Starting Address for Output BSET CDPLC ;Circular Addressing BSET SATD ;To Saturate Accumulator BSET FRCT ;To shift Accumulator left by one bit AMOV #000100h,XCDP ;Starting Address for coefficient H MOV #0h,BSAC ;Offset for circular Addressing of CDP MOV #N,BKC ;Size of Block for Circular Addressing MOV #(M+N-1)/2,BRC0 ;Initializing for local block repeat BR0+1 times MOV #N+1,T0 ;Offset to move pointer of AR0 back. RPTBLOCAL LOOP MPY *AR0-,*CDP+,AC0 :: MPY *AR2-,*CDP+,AC1 || RPT #N-3 MAC *AR0-,*CDP+,AC0 :: MAC *AR2-,*CDP+,AC1 MAC *(AR0+T0),*CDP+,AC0 :: MAC *(AR2+T0),*CDP+,AC1
; MOV HI(AC0),*AR1+ ;Storing Output LOOP MOV PAIR(HI(AC0)),DBL(*AR1+) ;Storing Output IDLE