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Modelsim® Advanced Verification Anddebugging

This document provides an overview of using ModelSim for Verilog and VHDL simulation and debugging. It describes creating projects with Verilog or VHDL design files, compiling and loading designs into the simulator, running simulations, and organizing projects using folders. Various dialog boxes and steps are illustrated through accompanying figures.

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rppvch
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25 views

Modelsim® Advanced Verification Anddebugging

This document provides an overview of using ModelSim for Verilog and VHDL simulation and debugging. It describes creating projects with Verilog or VHDL design files, compiling and loading designs into the simulator, running simulations, and organizing projects using folders. Various dialog boxes and steps are illustrated through accompanying figures.

Uploaded by

rppvch
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ModelSim Adv a n c e d V e r i f i c a t i o n a n d D eb ug gi n g

Basic simulation flow

Project flow

Multiple library flow

CREATING Verilog HDL PROJECT

Creating the working design library

Figure 1: The Welcome to ModelSim dialog

Compiling the design

Figure 2: The Create a New Library dialog

Compiling the design contd..

Figure 3: The newly created work library

Compiling the design

Figure 4: The Compile HDL Source Files dialog

Compiling the design contd..

Figure 5: Verilog modules compiled into the work library

Loading the design into the simulator

Figure 6: Loading the design with the Start Simulation dialog

Loading the design into the simulator contd..

Figure 7: Workspace tab showing a Verilog design

Running the simulation

Figure 8: Adding signals to the Wave window

Running the simulation contd..

Figure 9: Waves being drawn in the Wave window

CREATING VHDL PROJECT

Creating a new project

Figure 14: The Create Project dialog

Adding objects to the project

Figure 15: Adding new items to a project

Adding objects to the project contd..

Figure 16: The Add file to Project dialog

Changing compile order (VHDL)

Figure 17: Newly added project files display a ? for status

Changing compile order (VHDL) contd..

Figure 18: The Compile Order dialog box

Compiling and loading a design

Figure 19: The Library tab with an expanded library

Compiling and loading a design contd

Figure 20: The structure tab for the counter design unit

Organizing projects with folders

Figure 21: Adding a new folder to the project

Organizing projects with folders contd..

Figure 22: A folder in a project

Organizing projects with folders contd..

Figure 23: Creating a subfolder

Moving files to folders

Figure 24: A folder with a sub-folder

Moving files to folders contd..

Figure 25: Changing file location via the project settings dialog

Simulation Configurations

Figure 26: The Simulation Configuration dialog

Simulation Configurations contd..

Figure 27: A Simulation Configuration in the Project tab

Lesson wrap-up

Figure 28: Transcript shows options used for Simulation Configuration

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