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Sequential & Memory Review

The document discusses sequential and memory review from a previous lecture on microprocessor interfacing. It covers bits and bytes, memory types and access protocols, buses, memory mapping, and provides a block diagram of a basic computer system. Memory is described as an array of slots containing data addressed by an address. Read and write memory access protocols involve setting the address, chip select, read/write signals, and transferring data. The memory map of an AVR microcontroller is shown as an example.

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47 views

Sequential & Memory Review

The document discusses sequential and memory review from a previous lecture on microprocessor interfacing. It covers bits and bytes, memory types and access protocols, buses, memory mapping, and provides a block diagram of a basic computer system. Memory is described as an array of slots containing data addressed by an address. Read and write memory access protocols involve setting the address, chip select, read/write signals, and transferring data. The memory map of an AVR microcontroller is shown as an example.

Uploaded by

api-27015998
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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SEQUENTIAL & MEMORY

REVIEW
Lecture 02 Microprocessor Interfacing
Review [PREVIOUS LECTURE]
… Microcontroller
… Tools
… Programming Language
… Groups
… P – Requisite
Pre R i i RRequirements
i
Lecture Objectives
j
… Bits, Bytes,
… Memory, Data
… Address Space,
Space
… Memory Types,
… M
Memory Access
A Protocol
P l
… Buses
… Memory Map
… Block Diagram of Computer
Bits & Bytes
y
… The word bit is a shortening of the words "Binary
Binary
digIT”.
† Bitsare binaryy digits.
g A bit can hold the value 0 or 1.
† Bytes are made up of 8 bits each.

† Binary
y math works jjust like decimal math,, but each bit
can have a value of only 0 or 1.

There really is nothing more to it -- bits and


bytes
y are that simple.
p
Memory
y
… An array of slots, pigeon holes containing data
… Memory width, W: Number of bits in each slot
… Memory depth,
depth D: Number of slots
… Data lines = W
… Add
Address lines,
li N = ceil[
il[ log2(D)
l 2(D) ]
… Address space = 0..2^N-1
Total Address Space
p

N 2^N N 2^N
1 2 18 262144
2 4 20 1048576
3 8 22 4194304
4 16 24 16777216
5 32 28 268435456
6 64 30 1073741824
7 128 32 4294967296
8 256 40 1099511627776
10 1024 48 281474976710656
12 4096 56 72057594037927936
16 65536 64 18446744073709551616
Memory
y Types
yp
Memory
y Access Protocol: Read

E1: Set address


E2: Assert CS
E3: Assert RD
E4: Data Out (Memory)
E5: Read Data & Remove Address
E6: De-assert RD & cycle complete
E7 De-assert
E7: D t CS
E8: Chip in Tri-State
Memory
y Access Protocol: Write

E1: Set Data


E2: Set Address
E3: Assert CS
E4: Assert WR
E5: De-assert WR
E6: Remove Address cycle complete
E7:Remove Data
E8: De-assert CS
Buses
Memory
y Map
p
Memory
y Map
p [AVR ATMEGA16]

Program Memory
Buses,, Address,, Data & Control
Block Diagram
g of a Computer
p System
y

Memory System Buses Microprocessor Buses I/O System

Dynamic RAM (DRAM)


Printer
Static RAM (SRAM)
Serial Comm.
Cache
Floppy disk drive
Read only (ROM)
Hard disk drive
Flash memory
Mouse
EEPROM
CD-ROM drive
Pl tt
Plotter
Keyboard
Monitor
Scanner
DVD

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