Agenda

Introduction: SystemVerilog Motivation

Vassilios Gerousis, Infineon Technologies Accellera Technical Committee Chair

Session 3: SystemVerilog Assertions Language Tutorial

Bassam Tabbara, Novas Software

Tecnhology and User Experience

Alon Flaisher, Intel

Session 1: SystemVerilog for Design Language Tutorial

Johny Srouji, Intel

Using SystemVerilog Assertions and Testbench Together

Jon Michelson, Verification Central

User Experience
Matt Maidment, Intel

Session 4: SystemVerilog APIs

Doug Warmke, Model Technology

Session 2: SystemVerilog for Verification Language Tutorial

Tom Fitzpatrick, Synopsys

Session 5: SystemVerilog Momentum Verilog2001 to SystemVerilog

Stuart Sutherland, Sutherland HDL

User Experience
Faisal Haque, Verification Central
Lunch: 12:15 1:00pm

SystemVerilog Industry Support

Vassilios Gerousis, Infineon
End: 5:00pm

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SystemVerilog Assertions Language Overview

Dr. Bassam Tabbara Technical Manager, R&D Novas Software, Inc.

What is an Assertion?
A concise description of [un]desired behavior
0 req ack
Example intended behavior

After the request signal is asserted, the acknowledge signal must come 1 to 3 cycles later

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SystemVerilog and Assertions

Enhance SystemVerilog to support AssertionBased Verification
White-box (inside block) assertions Black-box (at interface boundaries) assertions

Syntactic compatibility
Easy to code directly in-line with RTL

Support for design and assertion reuse

Support for assertion binding to design from separate file

Monitoring the design

Concurrent (standalone) assertions Procedural (embedded) assertions
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SystemVerilog Assertion Goals

Expressiveness
Cover large set of design properties:
Block Implementation Block Interaction

Usability:
Easy to understand and use by:
Design Engineer Verification Engineer

Formalism:
Formal semantics to ensure correct analysis Consistent semantics between simulation and formal design validation approaches
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Concise and Expressive SVA

SVA Assertion
property req_ack; @(posedge clk) req ##[1:3] $rose(ack); endproperty as_req_ack: assert property (req_ack); always @(posedge req) begin repeat (1) @(posedge clk); fork: pos_pos begin @(posedge ack) $display("Assertion Success",$time); disable pos_pos; end begin repeat (2) @(posedge clk); $display("Assertion Failure",$time); disable pos_pos; end join end // always

req ack
Example intended behavior

HDL Assertion

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The Basics
4 Easy Lessons

Immediate assertions
assert ( expression ) action_block; action_block ::= [statement] [else statement]

Appears as a procedural statement Follows simulations semantics, like an if

if (expression) action_block;

Action block
Executes immediately Can contain system tasks to control severity, for example: $error, $warning,
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Concurrent assertions
assert property ( property_instance_or_spec ) action_block; action_block ::= [statement] [else statement]

Appears outside/inside procedural context Follows cycle semantics using sampled values Action block
Executes in reactive region Can contain system tasks to control severity, for example: $error, $warning,
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Assertion Sampling
Values sampled at end of previous Time Step
Time Step sample here
clock

input

clock edge (clocking event)

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Hierarchy of Assertion Constructs

Assertion Directives Property Declarations Sequential Regular Expressions Boolean Expressions
assert, cover, bind, declarative instantiation, procedural instantiation

disable iff, not, implication repetition,(cycle)delay, and, or, intersect, first_match, within, throughout <expr>, <function>, <temporal_edge_function>, ended, matched

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Congratulations !!!

Sequential Regular Expressions

Describing a sequence of events Sequences of Boolean expressions can be described with a specified time step in-between @(posedge clk) a ##1 b ##4 c ##[1:5] z;
z c b a clk
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Regular Expression Examples

Expression Range Repetition Basic sequencing

a b c

a b b b c a b b b b c
a ##1 b[*3:4] ##1 c Expression Non-Consecutive Counting Repetition

a ##1 b ##1 c ##1 z Sequence with Delay

a b

a
a ##1 b ##2 c

b b c

a ##1 b[*=2] ##1 c Expression Repetition Expression Goto Repetition

a b b b c
a ##1 b[*3] ##1 c

b b c

a ##1 b[*->2] ##1 c

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Sequences Encapsulate Behavior

Can be Declared
sequence <name>[(<args>)]; [@(<clocking>)] <sequence>; endsequence sequence s1(a,b); @(posedge clk) a[*2] ##3 b; endsequence

Sequences Can Be Built From Other Sequences

sequence s2; @(posedge clk) c ##1 d; endsequence sequence s3; @(posedge clk) s1(e,f) ##1 s2; endsequence

Operations to compose sequences

and, or, intersect, within, throughout

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Sequence Operations
Sequence Concatenation s1 s2 s1 ##1 s2 s1 and s2 Sequence Overlap s1 s2 s1 ##0 s2 First Match s1 first_match(s1) Sequence intersect s1 s2 s1 intersect s2 Sequence or s1 s2 s1 or s2 Sequence and s1 s2

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More Sequence Operations

Sequence Ended s1 s2 s1 ##1 s2.ended Temporal Edge Functions Expression throughout a Sequence

a
s1 a throughout s1

a
!a ##1 $rose(a);

a
a[*2] ##1 $fell(a)

Sequence within another Sequence s1 s2 s1 within s2

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Property Definition
Property Declaration: property
Declares property by name Formal parameters to enable property reuse Top Level Operators not desired/undesired disable iff reset |->, |=> precondition

Assertion Directives
assert checks that the property is never violated cover tracks all occurrences of property
property prop1(a,b,c,d); disable iff (reset) (a) |-> [not](b ##[2:3]c ##1 d); endproperty assert1: assert prop1 (g1, h2, hxl, in3);
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Property implication
sequence_expr |-> [not] sequence_expr sequence_expr |=> [not] sequence_expr

|-> is overlapping implication |=> is non-overlapping implication same as:

sequence_expr ##1 `true|-> [not] sequence_expr

Most commonly used to attach a precondition to sequence evaluation

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Multiple Clock Support

Clocking event controls must be specified for each subsequence
Multi-Clock Sequence Concatenation s2 s1 @(clk1) s1 ## @(clk2) s2 Multi-Clock Sequence Matching s2 s1 s3

s1 ##1 s2.matched ##1 s3

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Manipulating Data: Local Dynamic Variables

Declared Locally within Sequence/Property
New copy of variable for each sequence invocation

Assigned anywhere in the sequence Value of assigned variable remains stable until reassigned in a sequence
Local Dynamic Variable Example

valid in out EA BF EB
property e; int x; (valid,(x=in))|=> ##5(out==(x+1)); endproperty
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C0

Embedding Concurrent Assertions

sequence s1; (req && !gnt)[*0:5] ##1 gnt && req ##1 !req ; endsequence Automatically Updates always @(posedge clk or negedge reset) Enabling Condition as if(reset == 0) do_reset; Design Changes else if (mode == 1) Infers clock from case(st) instantiation REQ: if (!arb) if (foo) Requires User to Update st <= REQ2; Manually as Design PA: assert property (s1); Changes property p1; @(posedge clk) ((reset == 1) && (mode == 1) && (st == REQ) && (!arb) && (foo)) => s1; endproperty DA: assert property (p1);
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Bind statement
bind module_or_instance_name instantiation;

No semantic changes to assertion Minimal change to design code Assertions included in the instantiation Allows binding a module, program and interface instance Mechanism to attach verification IP to module or module instance

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Bind statement
bind module_or_instance_name instantiation; Top
cpu1 module cpu(a,b); reg c; ... endmodule cpu2 module cpu(a,b); reg c; ... endmodule
module/instance name

bind

cpu cpu_props cpu_rules1(a,b,c);

instance name program name

program cpu_props(input d,e,f);

assert property (d ##1 e |=> f[*3]);

endprogram

Equivalent to: assert property (top.cpu1.a ##1 top.cpu1.b |=> top.cpu1.c[*3]); assert property (top.cpu2.a ##1 top.cpu2.b |=> top.cpu2.c[*3]); or cpu_props cpu_rules1(a,b,c); // in module cpu
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010

010

FF1 b

FF2 c

sample here

drive here
Preponed

clk

clock trigger

sample here
Active

assign #0 gclk = clk; always @(posedge gclk) b = a; // FF1 always @(posedge clk) c = b; // FF2 clocking @(posedge clk) sequence sa; !a ##1 a ##1 !a; endsequence sequence sc; !c ##1 c ##1 !c; endsequence property p sa => [2] sc; endproperty

Inactive

NBA

evaluate here

Observe

Reactive

assert property(p) pass_statement; else fail_statement;

react here

Postponed

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SystemVerilog Assertions Summary

Use clocked/sampled semantics for signals
Ensure compatibility with formal & synthesis tools Avoid race conditions

Declarative assertions add flexibility

Monitoring and evaluation Reuse

Support design/assertion IP creation and reuse Enhanced scheduling allows building reactive testbenches Enhanced coverage of functional spec
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