Getting Started with SystemC UVM

Verication in SystemC Perspective

Puneet Goel
Coverify Systems Technology

April 2012

overify C

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

Introduction
UVM stands for Universal Verication Methodology UVM is the Accellera approved standard methodology for verication UVM is primarily coded in SystemVerilog In November 2011, Cadence released UVM Multi-language package on UVM website http://uvmworld.com
The package contains a partial port of UVM Library in SystemC and e

In Feburary 2012, Mentor Graphics released opensource implementation of uvm::connect, and named the library UVMC Both UVM-ML and UVMC have been released under Apache License
Getting Started with SystemC UVM

overify C
2 / 22

UVM Testbench
Test Layer

Testcase

Command Functional Sequence Layer Layer Layer

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

Figure: UVM Testbench Infrastructure

overify C
Getting Started with SystemC UVM 3 / 22

SystemC UVM Testbench

Test Layer

Testcase

Command Functional Sequence Layer Layer Layer

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

Figure: Currently Supported by SystemC UVM

overify C
Getting Started with SystemC UVM 4 / 22

SystemC UVM Testbench

Test Layer

Testcase

Command Functional Sequence Layer Layer Layer

Sequencer

Constrained Randomization

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

Figure: Currently Supported by SystemC UVM

overify C
Getting Started with SystemC UVM 4 / 22

SystemC UVM Testbench

Test Layer

Testcase

Register Abstraction Layer

Command Functional Sequence Layer Layer Layer

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

Figure: Currently Supported by SystemC UVM

overify C
Getting Started with SystemC UVM 4 / 22

In this section . . .

SystemC Perspective Why SystemC for Verication UVM for SystemC

overify C
Getting Started with SystemC UVM SystemC Perspective 5 / 22

Why SystemC?

A couple of questions that obviously prop are: Is not verication meant to be done using HVLs like Specman/Vera/SystemVerilog etc? Is not UVM primarily coded in SystemVerilog? What advantage does SystemC has over SystemVerilog?

overify C
Getting Started with SystemC UVM SystemC Perspective 6 / 22

Why SystemC?

A couple of questions that obviously prop are: Is not verication meant to be done using HVLs like Specman/Vera/SystemVerilog etc? Is not UVM primarily coded in SystemVerilog? What advantage does SystemC has over SystemVerilog?

overify C
Getting Started with SystemC UVM SystemC Perspective 6 / 22

Why SystemC?

A couple of questions that obviously prop are: Is not verication meant to be done using HVLs like Specman/Vera/SystemVerilog etc? Is not UVM primarily coded in SystemVerilog? What advantage does SystemC has over SystemVerilog?

overify C
Getting Started with SystemC UVM SystemC Perspective 6 / 22

SystemC UVM Use Cases

Command Functional Sequence Layer Layer Layer

Verication of ESL components coded in SystemC using SystemVerilog based testbenches Using SystemC Driver and Monitor components in SystemVerilog testbench SystemC model used as golden reference model for verication

Test Layer

Testcase

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

overify C
Getting Started with SystemC UVM SystemC Perspective 7 / 22

SystemC UVM Use Cases

Command Functional Sequence Layer Layer Layer

Verication of ESL components coded in SystemC using SystemVerilog based testbenches Using SystemC Driver and Monitor components in SystemVerilog testbench SystemC model used as golden reference model for verication

Test Layer

Testcase

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

overify C
Getting Started with SystemC UVM SystemC Perspective 7 / 22

SystemC UVM Use Cases

Command Functional Sequence Layer Layer Layer

Verication of ESL components coded in SystemC using SystemVerilog based testbenches Using SystemC Driver and Monitor components in SystemVerilog testbench SystemC model used as golden reference model for verication

Test Layer

Testcase

Sequencer

Checker Functional Coverage

Transactor

Monitor

Driver

Collector

Assertions

Collector

Signal Layer

Design Under Test

overify C
Getting Started with SystemC UVM SystemC Perspective 7 / 22

SystemC for coding Reference Model

SystemVerilog is a Hardware Design and Verication Language
Often your DUT (or a part of it) would be coded using verilog Coding reference model in the same language as the language in which your design has been coded is often a bad idea

When designers and verication engineers use same language, there is a risk that they might share code Or might make same mistakes they would have the same set of language gotchas to deal with

overify C
Getting Started with SystemC UVM SystemC Perspective 8 / 22

SystemC for coding Reference Model

SystemVerilog is a Hardware Design and Verication Language
Often your DUT (or a part of it) would be coded using verilog Coding reference model in the same language as the language in which your design has been coded is often a bad idea

When designers and verication engineers use same language, there is a risk that they might share code Or might make same mistakes they would have the same set of language gotchas to deal with

overify C
Getting Started with SystemC UVM SystemC Perspective 8 / 22

SystemC for coding Reference Model

SystemVerilog is a Hardware Design and Verication Language
Often your DUT (or a part of it) would be coded using verilog Coding reference model in the same language as the language in which your design has been coded is often a bad idea

When designers and verication engineers use same language, there is a risk that they might share code Or might make same mistakes they would have the same set of language gotchas to deal with

overify C
Getting Started with SystemC UVM SystemC Perspective 8 / 22

SystemC for coding Reference Model

SystemVerilog is a Hardware Design and Verication Language
Often your DUT (or a part of it) would be coded using verilog Coding reference model in the same language as the language in which your design has been coded is often a bad idea

When designers and verication engineers use same language, there is a risk that they might share code Or might make same mistakes they would have the same set of language gotchas to deal with

overify C
Getting Started with SystemC UVM SystemC Perspective 8 / 22

SystemC for coding Reference Model

SystemVerilog is a Hardware Design and Verication Language
Often your DUT (or a part of it) would be coded using verilog Coding reference model in the same language as the language in which your design has been coded is often a bad idea

When designers and verication engineers use same language, there is a risk that they might share code Or might make same mistakes they would have the same set of language gotchas to deal with

overify C
Getting Started with SystemC UVM SystemC Perspective 8 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

Generic Library

Though SystemVerilog supports parameterized classes, it does not support function and operator overloading As a result, SystemVerilog lacks a generic algorithmic library
For example if you develop a sort function in systemverilog that works for builtin number types, you can not generalize this function to work on user-dened data types

In comparison SystemC, since it is built over C++, has generic libraries such as STL and boost
These libraries come in handy when you are modeling at behavioral level Also since C++ has a much bigger user-base, these libraries are well-tested and therefor are ideal for creating reference models

overify C
Getting Started with SystemC UVM SystemC Perspective 9 / 22

In this section . . .

SystemC Perspective UVM for SystemC UVM Constructs

overify C
Getting Started with SystemC UVM UVM for SystemC 10 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

SystemC UVM Features

Conguration Global conguration object that records conguration for UVM components even before they are constructed. Helpful for creating object specic behaviour. Factory Implementation of Abstract and Concrete factories in C++. Useful for transaction and component creation. Packing Packer class implementation. Enables passing data transactions between SystemC and SystemVerilog. Phasing Enables synchronized build, congure, connect, run, report operations. Connect Enables connections between SystemVerilog and SystemC components. Conversion Package for conversion between SystemC and SystemVerilog standard data types.
overify C
Getting Started with SystemC UVM UVM for SystemC 11 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

UVM Components as well as SystemC models tend to be hierarchical in nature Different components in a hierarchy are bound by ports and channels
Ports and Channels form the interface of a component (or module) Any other component (or module) that wants to access a given module, does it through the interface

Such structural models give rise to rigidity

A change in one module, disturbs all the modules that are bound to this module

overify C
Getting Started with SystemC UVM UVM for SystemC 12 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:
component A component B component C

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:
component A component B component C

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:
component A component B component C

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

In UVM testbenches and in SystemC models, the problem is compunded by availability of various forms of comonents modeled at different abstraction levels For example various models may be available for a given component, including:
component A component B component C

untimed loosely time cycle accurate a combination

overify C
Getting Started with SystemC UVM UVM for SystemC 13 / 22

Harnessing the UVM Factory

The OOP paradigm comes to our rescue here, in form of polymorphism

OOP principles tell us not to program to the implementation Instead program to the interfaces, we are told

overify C
Getting Started with SystemC UVM UVM for SystemC 14 / 22

Harnessing the UVM Factory

The OOP paradigm comes to our rescue here, in form of polymorphism
Component A Package UVM component A Component B Package UVM UVM UVM component B component B component B Component C Package UVM UVM UVM component C component B component B component B service component A service

OOP principles tell us not to program to the implementation Instead program to the interfaces, we are told

overify C
Getting Started with SystemC UVM UVM for SystemC 14 / 22

Harnessing the UVM Factory

The OOP paradigm comes to our rescue here, in form of polymorphism
Component A Package UVM component A Component B Package UVM UVM UVM component B component B component B Component C Package UVM UVM UVM component C component B component B component B service component A service

OOP principles tell us not to program to the implementation Instead program to the interfaces, we are told

overify C
Getting Started with SystemC UVM UVM for SystemC 14 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp A

While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

Comp B
Cycle Accurate

<<interface>>

Comp B

Comp B
Loosely Timed

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp A

While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

Comp B
Cycle Accurate

<<interface>>

Comp B

Comp B
Loosely Timed

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

Logical application of OOP paradigm makes our code independent of the implementation details instead the compenents are now bound to an interface (virtual base class) Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp A

While all other methods (class functions) can be made virtual, the constructor can not be As a result, at the time of creating the component, a particular implementation has to be specied Object generation spoils much of what polymorphism had to offer

Comp B
Cycle Accurate

<<interface>>

Comp B

Comp B
Loosely Timed

overify C
Getting Started with SystemC UVM UVM for SystemC 15 / 22

Harnessing the UVM Factory

This is exactly where UVM Factory comes to our rescue: UVM Factory is an implementation of the popular generational design patterns Abstract Factory and Concrete Factory UVM (concrete) Factory is a global singleton object Base classes as well as derived classes are registered with the global factory Conguration interface is provided for any base class, so that when you create an object of the base class, the actual object created is for a derived class as per the conguration
overify C
Getting Started with SystemC UVM UVM for SystemC 16 / 22

Harnessing the UVM Factory

This is exactly where UVM Factory comes to our rescue: UVM Factory is an implementation of the popular generational design patterns Abstract Factory and Concrete Factory UVM (concrete) Factory is a global singleton object Base classes as well as derived classes are registered with the global factory Conguration interface is provided for any base class, so that when you create an object of the base class, the actual object created is for a derived class as per the conguration
overify C
Getting Started with SystemC UVM UVM for SystemC 16 / 22

Harnessing the UVM Factory

This is exactly where UVM Factory comes to our rescue: UVM Factory is an implementation of the popular generational design patterns Abstract Factory and Concrete Factory UVM (concrete) Factory is a global singleton object Base classes as well as derived classes are registered with the global factory Conguration interface is provided for any base class, so that when you create an object of the base class, the actual object created is for a derived class as per the conguration

Comp A UVM Factory

+ create()
<<interface>> <<interface>>

Comp B

UVM Factory

Comp B
Loosely Timed

Comp B
Cycle Accurate

overify C
Getting Started with SystemC UVM UVM for SystemC 16 / 22

Harnessing the UVM Factory

This is exactly where UVM Factory comes to our rescue: UVM Factory is an implementation of the popular generational design patterns Abstract Factory and Concrete Factory UVM (concrete) Factory is a global singleton object Base classes as well as derived classes are registered with the global factory Conguration interface is provided for any base class, so that when you create an object of the base class, the actual object created is for a derived class as per the conguration

Comp A UVM Factory

+ create()
<<interface>> <<interface>>

Comp B

UVM Factory

Comp B
Loosely Timed

Comp B
Cycle Accurate

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Getting Started with SystemC UVM UVM for SystemC 16 / 22

Harnessing the UVM Factory

This is exactly where UVM Factory comes to our rescue: UVM Factory is an implementation of the popular generational design patterns Abstract Factory and Concrete Factory UVM (concrete) Factory is a global singleton object Base classes as well as derived classes are registered with the global factory Conguration interface is provided for any base class, so that when you create an object of the base class, the actual object created is for a derived class as per the conguration

Comp A UVM Factory

+ create()
<<interface>> <<interface>>

Comp B

UVM Factory

Comp B
Loosely Timed

Comp B
Cycle Accurate

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Getting Started with SystemC UVM UVM for SystemC 16 / 22

UVM Phases
SystemC has only a few phases. In contrast, UVM has a very elaborate phase sequence.
VerilogElaboration End of Elaboration Start of Simulation UVM Build Phase UVM Connect Phase SystemC Elaboration End of Elaboration Start of Simulation UVM Run Phase UVM Extract Phase UVM Check Phase UVM Report Phase End of Simulation Simulation Run

Note that Start of Elaboration and Start of Simulation etc are PLI hooks in Verilog and similarly are function hooks in SystemC The Build and Connect phase in UVM happen at ZERO simulation time

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Getting Started with SystemC UVM UVM for SystemC 17 / 22

UVM Phases
SystemC has only a few phases. In contrast, UVM has a very elaborate phase sequence.
VerilogElaboration End of Elaboration Start of Simulation UVM Build Phase UVM Connect Phase SystemC Elaboration End of Elaboration Start of Simulation UVM Run Phase UVM Extract Phase UVM Check Phase UVM Report Phase End of Simulation Simulation Run

Note that Start of Elaboration and Start of Simulation etc are PLI hooks in Verilog and similarly are function hooks in SystemC The Build and Connect phase in UVM happen at ZERO simulation time

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Getting Started with SystemC UVM UVM for SystemC 17 / 22

Conguring a Build

Not all the instances of a class (UVM Component) may be exactly same in behaviour There may be a need to congure a UVM Component Often, it might be useful to build a UVM component while taking some conguration parameters into account

Processor Master

Processor Master

Processor Master Global Memory

Routing Node

Routing Node

Routing Node

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Figure: Asymmetric Architecture

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Getting Started with SystemC UVM UVM for SystemC 18 / 22

Conguring a Build

Not all the instances of a class (UVM Component) may be exactly same in behaviour There may be a need to congure a UVM Component Often, it might be useful to build a UVM component while taking some conguration parameters into account

Processor Master

Processor Master

Processor Master Global Memory

Routing Node

Routing Node

Routing Node

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Figure: Asymmetric Architecture

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Getting Started with SystemC UVM UVM for SystemC 18 / 22

Conguring a Build

Not all the instances of a class (UVM Component) may be exactly same in behaviour There may be a need to congure a UVM Component Often, it might be useful to build a UVM component while taking some conguration parameters into account

Processor Master

Processor Master

Processor Master Global Memory

Routing Node

Routing Node

Routing Node

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Processor Master

Processor Master

Processor Master

Routing Node

Routing Node

Routing Node

Global IO

Figure: Asymmetric Architecture

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Getting Started with SystemC UVM UVM for SystemC 18 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

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Getting Started with SystemC UVM UVM for SystemC 19 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

overify C
Getting Started with SystemC UVM UVM for SystemC 19 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

overify C
Getting Started with SystemC UVM UVM for SystemC 19 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

overify C
Getting Started with SystemC UVM UVM for SystemC 19 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

overify C
Getting Started with SystemC UVM UVM for SystemC 19 / 22

Conguring the Build UVM Way

The Congure object provided by UVM is useful for providing conguration parameters in the build phase The parameters are tied with the hierarchical name of the component being built. This is useful for enabling instance-specic custom behaviour for a component. Caveat Note that the conguration object needs the same elds on pthe congure and component side. This results in a strong binding (in the software sense). Sometimes it results in confusing situations (because of typos in the congure parameters).

Use with care

overify C
Getting Started with SystemC UVM UVM for SystemC 19 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
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Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
overify C
Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
overify C
Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
overify C
Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
overify C
Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
overify C
Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Transactions
UVM-SC library provides a base class for creating a transaction (called sequence item in UVM) The UVM-SC implementation lacks CPP macros to automatically create virtual methods for print, pack, unpack, copy and compare operations UVM-SC makes it mendatory for the user to implement these functions A transaction class can be registered with the UVM factory, making it possible to generate transaction objects using the factory UVM-SC depends on the pack/unpack operations to send transactions across the language boundaries A user must make sure that pack/unpack methods for the transaction class in SystemC and SystemVerilog remain in sync Caveat When you pack data in SystemVerilog or in SystemC, you loose the control bits for any 4-valued logic data.
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Getting Started with SystemC UVM UVM for SystemC 20 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

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Getting Started with SystemC UVM UVM for SystemC 21 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

overify C
Getting Started with SystemC UVM UVM for SystemC 21 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

overify C
Getting Started with SystemC UVM UVM for SystemC 21 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

overify C
Getting Started with SystemC UVM UVM for SystemC 21 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

overify C
Getting Started with SystemC UVM UVM for SystemC 21 / 22

UVM Connect Library

The UVM Connect package from Mentor Graphics is built on top of UVM-SC package by Cadence It provides an opensource implementation for connecting SystemVerilog and SystemC ports Also implements conversion between standard SystemC and SystemVerilog data types UVMC package does not require you to create a UVM transaction on the SystemC side
Instead it provides macros to automatically dene the pack/unpack functionality on SystemC side Since these macros dene functions (not class methods) for the pack/unpack functionality, UVMC does not bind your SystemC transaction class to any base class

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Getting Started with SystemC UVM UVM for SystemC 21 / 22

Thank You!

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