Scribd
Upload
51 views7 pages

ECE380 Digital Logic: - Master-Slave Flip-Flip - Edge-Triggered Flip-Flop

The document discusses different types of flip-flops including master-slave, edge-triggered, T, and JK flip-flops. A master-slave flip-flop consists of two latches where the master follows the input while the clock is high and the slave follows the master when the clock is low, changing state only on the negative edge. An edge-triggered flip-flop changes state on either the positive or negative edge of the clock. T and JK flip-flops can toggle or change the output state depending on their control inputs.

Uploaded by

MoHsin Kh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
51 views7 pages

ECE380 Digital Logic: - Master-Slave Flip-Flip - Edge-Triggered Flip-Flop

The document discusses different types of flip-flops including master-slave, edge-triggered, T, and JK flip-flops. A master-slave flip-flop consists of two latches where the master follows the input while the clock is high and the slave follows the master when the clock is low, changing state only on the negative edge. An edge-triggered flip-flop changes state on either the positive or negative edge of the clock. T and JK flip-flops can toggle or change the output state depending on their control inputs.

Uploaded by

MoHsin Kh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

ECE380 Digital Logic

Flip-Flops, Registers and Counters: Flip-Flops

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 25-1

Flip-flops
The gated latch circuits presented are level sensitive and can change states more than once during the active period of the clock signal Circuits (storage elements) that can change their state no more than once during a clock period are also useful Two types of circuits with such behavior
Master-slave flip-flip Edge-triggered flip-flop
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-2

Master-slave D flip-flop
Consists of 2 gated D latches
The first, master, changes its state while clock=1 The second, slave, changes its state while clock=0
Master D Clock D Q Q Slave m D Q Qs

Q Q

Clk Q

Clk Q

38 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-3

Master-slave D flip-flop
When clock=1, the master tracks the values of the D input signal and the slave does not change When the clock signal changes to 0, the master stage stops following the changes in the D input signal At the same time, the slave stage responds to the value of Qm and changes states accordingly Since Qm does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle From an output point of view, the circuit changes Qs (its output) at the negative edge of the clock signal
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-4

Thus Qm follows any changes in D and Qs remains constant

Master-slave D flip-flop
Clock D Qm Q = Qs D clock Q Q

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 25-5

Edge-triggered flip-flop
A circuit, similar in functionality to the master-slave D flip-flop, can be constructed with 6 NAND gates
1 P3 P1 5 Q clock D Q Q

2 Clock 3

P2

Positive-edge-triggered D type flip-flop P4 24 transistors


Dr. D. J. Jackson Lecture 25-6

Electrical & Computer Engineering

Edge-triggered flip-flop
The previous circuit responds on the positive edge of the clock signal A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates
D clock Q Q clock D Q Q

Positive-edge-triggered D type flip-flop

Negative-edge-triggered D type flip-flop

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 25-7

Comparing D storage elements


D clock D Q Qa clock Qb D Qa Qc Q b Q c

clk Q D Q Q D Q Q

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 25-8

Clear and preset inputs


It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop Practical flip-flops often have preset and clear inputs
Generally, these inputs are asynchronous (they do not depend on the clock signal)
Preset D clock Clear
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-9

Q Q

As long as Preset=0, Q=1 As long as Clear=0, Q=0

T flip-flop
Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented Feedback connections make the input signal D equal to the value of Q or Q under control of a signal labeled T

D T Clock
Electrical & Computer Engineering

Q Q

Q Q

Dr. D. J. Jackson Lecture 25-10

T flip-flop
The name T derives from the behavior of the circuit, which toggles its state when T=1
This feature makes the T flip-flop a useful element when constructing counter circuits T Q(t+1) 0 Q(t) 1 Q(t)
Clock T Q T clock
Electrical & Computer Engineering

Q Q

Positive edge triggered


Dr. D. J. Jackson Lecture 25-11

JK flip-flop
The JK flip-flop can also be derived from the basic D flip-flop such that
D=JQ+KQ

The JK flip-flop combines aspects of the SR and the T flip-flop


It behaves as the SR flip-flop (where J=S and K=R) for all values except J=K=1 For J=K=1, it toggles like the T flip-flop

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 25-12

JK flip-flop
J D Q K Clock Q Q Q

J 0 0 1 1

K Q(t+1) 0 Q(t) 1 0 1 0 1 Q(t)


clock

J K

Q Q Positive edge triggered


Dr. D. J. Jackson Lecture 25-13

Electrical & Computer Engineering

JK flip-flop timing diagram


Complete the following timing diagram
Clk K J Q Q 1 0 1 0 1 0 1 0 1 0

Time
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 25-14

You might also like