Laboratory in Automatic Control Lab10

Automatic Control Lab 10

Uploaded by

Peter Finzell

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

91 views

Laboratory in Automatic Control Lab10

Automatic Control Lab 10

Uploaded by

Peter Finzell

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

You are on page 1/ 16

Laboratory in Automatic Control

LAB 10
System Design Using Classical Methods
Design a Lead Compensator (1/8)
As shown in the following figure, desire a steady-state error
of less than 10% to a ramp input, Kv=10 and the lead
compensator to meet certain performance specifications: (1)
settling time (with a 2% criterion) Ts<=3 seconds, and (2)
percent overshoot for a step input <=10%.
Design a Lead Compensator (2/8)
The steady-state error to a unit ramp input is

where

Consider a simple gain controller

then

1
ss
v
e
K
=
( )
( )( )
( )
0
lim
5 10 50
c c
v
s
G s G s
K s
s s s

= =
+ +
( )
c
G s K =
10 500
50
v
K
K K = = =
Design a Lead Compensator (3/8)
Solving for and using

We thus obtain the phase margin requirement:
,
n
e
( )
2
1
. . % 100exp 10 0.59
4
3 2.26
s n
n
PO
T
,t ,
,
e
,e

= = =
= = =
60
0.01
pm
,
| =
Textbook P.521
Design a Lead Compensator (4/8)
MATLAB code
k=500;
numg=[1]; deng=[1 15 50 0];
sysg=tf(numg,deng); sys=k*sysg;
[Gm,Pm,Wcg,Wcp]=margin(sys); % Compute phase margin.
Phi=(60-Pm)*pi/180; % Additional phase lead.
alpha=(1+sin(Phi))/(1-sin(Phi)); %Compute alpha. Textbook P.591
[mag,phase,w]=bode(sys);
mag_save(1,:)=mag(:,:,:);
M=-10*log10(alpha)*ones(length(w),1);
semilogx(w,20*log10(mag_save),w,M,'--')
xlabel('Frequency (rad/sec)'),ylabel('Magnitude (dB)')
hold on
semilogx([0.9 9 90],[20 0 -20],'--'),grid on
Design a Lead Compensator (5/8)

Uncompensated
( )
( )
3.
25
5
c
K s
G s
s
+
=
+
10logo
Design a Lead Compensator (6/8)
MATLAB code
numg=[1];deng=[1 15 50 0];dengc=[1 25];
for K=1:50:2000
numgc=K*[1 3.5];sysg=tf(numg,deng);sysgc=tf(numgc,dengc);
sys1=series(sysgc,sysg);
[Gm,Pm,Wg,Wc]=margin(sys1);
if (Pm<=60)
k1=K
numgc=k1*[1 3.5]; sysgc=tf(numgc,dengc);
sys2=series(sysgc,sysg);margin(sys2); break
end
end
sys3=feedback(sys2,[1]);
t=[0:0.01:2];
figure,step(sys3,t),hold on
plot(t,1.02,'-',t,0.98,'-'),ylabel ('y(t)')
Design a Lead Compensator (7/8)

Design a Lead Compensator (8/8)

The final lead compensator design is

Resulting in a 20% steady-state error to a ramp input

( )
( )
1801 3.5
25
c
s
G s
s
+
=
+
Design a Lag Compensator (1/6)
As shown in the following figure, desire a steady-state error
of less than 10% to a ramp input, Kv=10 and the lag
compensator to meet certain performance specifications: (1)
settling time (with a 2% criterion) Ts<=3 seconds, and (2)
percent overshoot for a step input <=10%.

Design a Lag Compensator (2/6)
Solving for and using

We thus obtain the phase margin requirement
( )
2
1
. . % 100exp 10 0.59
4
3 2.26
s n
n
PO
T
,t ,
,
e
,e

= = =
= = =
60
0.01
pm
,
| =
,
n
e
Design a Lag Compensator (3/6)
MATLAB code
numg=[1]; deng=[1 15 50 0];
sysg=tf(numg,deng);
clf; % Clear current figure
rlocus(sysg); hold on
zeta=0.5912; wn=2.2555;
x=[-10:0.1:-zeta*wn];
y=-(sqrt(1-zeta^2)/zeta)*x;
xc=[-10:0.1:-zeta*wn];
c=sqrt(wn^2-xc.^2);
plot(x,y,':',x,-y,':',xc,c,':',xc,-c,':')
axis([-15,1,-10,10]);
rlocfind(sysg)
Plot performance regions on locus.
Design a Lag Compensator (4/6)

Compute

Select

Uncompensated K
10
0.1
103
1
0.1
comp
uncomp
v
v
K
K
z
p z
p
o
o
= = ~
= =
0.1
0.01
z
p
=

Design a Lag Compensator (5/6)

MATLAB code
numg=[1]; deng=[1 15 50 0];
sysg=tf(numg,deng);
numgc=[1 0.1]; dengc=[1 0.01];
sysgc=tf(numgc,dengc);
sys=series(sysgc,sysg);
clf;rlocus(sysg); hold on
zeta=0.5912; wn=2.2555;
x=[-10:0.1:-zeta*wn];
y=-(sqrt(1-zeta^2)/zeta)*x;
xc=[-10:0.1:-zeta*wn];
c=sqrt(wn^2-xc.^2);
plot(x,y,':',x,-y,':',xc,c,':',xc,-c,':')
axis([-15,1,-10,10]);
Compensated root locus remains
almost unchanged.
Design a Lag Compensator (6/6)
MATLAB code
K=100;
numg=[1]; deng=[1 15 50 0];
sysg=tf(numg,deng);
numgc=K*[1 0.1]; dengc=[1 0.01];
sysgc=tf(numgc,dengc);
syso=series(sysgc,sysg);
sys=feedback(syso,[1]);
step(sys);
[gm,pm,wg,wp]=margin(syso);
pm
Lab 10 Homework
Consider the control system shown in Figure. Design a lead
compensator using bode plot methods to meet the following
specifications: (1) percent overshoot for a step input <=20%.

and (2) settling time (with a 2% criterion) less than 4
seconds for a unit step input.