Computer Architecture II: Specialized: Fall 2001
Computer Architecture II: Specialized: Fall 2001
/Rowan University
Plan
Recall: Floating Point Representation
IEEE 754 Standard IA-32 Data Types
Recall: FP Representation
Sign bit Biased Exponent
8 bits Sign of Mantissa
Significand/Mantissa/Fraction
23 bits
Single Precision
32 8
Single Extended
>= 43 >= 11
Double Precision
64 11
Double Extended
>= 79 >= 15
Exponent bias
Max exponent Min exponent Number range (base 10) Mantissa width (bits) No. of exponents No. of fractions No. of values
127
127 -126 10 , 10 23 254 2
23 31 -38 +38
Unspecified
>= 1023 <= -1022 Unspecified >= 31 Unspecified Unspecified Unspecified 10
1023
1023 -1022
-308 +308
Unspecified
>= 16383 <= -16382 Unspecified >= 63 Unspecified Unspecified
63
, 10
52 2046 2
52
1.98 x 2
1.98 x 2
Unspecified
Sign
0 1 0 1 0 or 1 0 or 1 0 1
Biased Exponent
0 0 255 (all 1s) 255 (all 1s) 255 (all 1s) 255 (all 1s) 0 < e < 255 0 < e < 255
Fraction
0 0 0 0 neq 0 neq 0 f f
Value
0 -0 Infinity -Infinity NaN NaN 2
e-127
(1.f) (1.f)
-2
e-127
Positive denormalized
Negative denormalized
0
1
0
0
f neq 0
f neq 0
e-126
(0.f)
(0.f)
-2
e-126
FP Addition/Subtraction
FP Multiplication
FP Division
References
William Stallings, Computer Organization and Architecture, 5th Edition, Prentice-Hall, 2000. ftp://ftp.prenhall.com/pub/esm/computer_s cience.s-041/stallings/Slides/COA5eSlides/ IA-32 Intel Architecture Software Developers Manual Volume 1: Basic Architecture http://www.intel.com/home/pentium4/
Summary