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Computer Architecture II: Specialized: Fall 2001

This document outlines a lecture on computer architecture and floating point representation. It discusses the IEEE 754 standard for floating point numbers and its parameters for single and double precision. It also covers floating point representation in the IA-32 architecture and arithmetic operations like addition, subtraction, multiplication and division according to the IEEE 754 standard. Finally, it lists references for further information.

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0% found this document useful (0 votes)
35 views

Computer Architecture II: Specialized: Fall 2001

This document outlines a lecture on computer architecture and floating point representation. It discusses the IEEE 754 standard for floating point numbers and its parameters for single and double precision. It also covers floating point representation in the IA-32 architecture and arithmetic operations like addition, subtraction, multiplication and division according to the IEEE 754 standard. Finally, it lists references for further information.

Uploaded by

rajeevrajkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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S. Mandayam/ CompArch2/ECE Dept.

/Rowan University

Computer Architecture II: Specialized


0909.444.01/02

Fall 2001 Lecture 2 October 31, 2001


John L. Schmalzel Shreekanth Mandayam
ECE Department Rowan University
http://engineering.rowan.edu/~shreek/fall01/comparch2/

S. Mandayam/ CompArch2/ECE Dept./Rowan University

Plan
Recall: Floating Point Representation
IEEE 754 Standard IA-32 Data Types

Floating Point Arithmetic


IEEE 754 implementation

Class Discussion: Presentation Project Selection

S. Mandayam/ CompArch2/ECE Dept./Rowan University

Recall: FP Representation
Sign bit Biased Exponent
8 bits Sign of Mantissa

Significand/Mantissa/Fraction
23 bits

S. Mandayam/ CompArch2/ECE Dept./Rowan University

Floating Point: Expressible Numbers

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IEEE 754 Standard


Parameter
Word width (bits) Exponent width (bits)

Single Precision
32 8

Single Extended
>= 43 >= 11

Double Precision
64 11

Double Extended
>= 79 >= 15

Exponent bias
Max exponent Min exponent Number range (base 10) Mantissa width (bits) No. of exponents No. of fractions No. of values

127
127 -126 10 , 10 23 254 2
23 31 -38 +38

Unspecified
>= 1023 <= -1022 Unspecified >= 31 Unspecified Unspecified Unspecified 10

1023
1023 -1022
-308 +308

Unspecified
>= 16383 <= -16382 Unspecified >= 63 Unspecified Unspecified
63

, 10

52 2046 2
52

1.98 x 2

1.98 x 2

Unspecified

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IEEE 754 Numbers and NaNs


Number
Positive zero Negative zero Plus infinity Minus infinity Quiet NaN Signaling NaN Positive normalized nonzero Negative normalized nonzero

Sign
0 1 0 1 0 or 1 0 or 1 0 1

Biased Exponent
0 0 255 (all 1s) 255 (all 1s) 255 (all 1s) 255 (all 1s) 0 < e < 255 0 < e < 255

Fraction
0 0 0 0 neq 0 neq 0 f f

Value
0 -0 Infinity -Infinity NaN NaN 2
e-127

(1.f) (1.f)

-2

e-127

Positive denormalized
Negative denormalized

0
1

0
0

f neq 0
f neq 0

e-126

(0.f)
(0.f)

-2

e-126

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IA-32 Architecture: Data Types

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IA-32 Architecture: Numeric Data Types

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IA-32 Architecture: Numeric Data Types

S. Mandayam/ CompArch2/ECE Dept./Rowan University

IA-32: Numbers and NaNs

S. Mandayam/ CompArch2/ECE Dept./Rowan University

FP Addition/Subtraction

S. Mandayam/ CompArch2/ECE Dept./Rowan University

FP Multiplication

S. Mandayam/ CompArch2/ECE Dept./Rowan University

FP Division

S. Mandayam/ CompArch2/ECE Dept./Rowan University

References
William Stallings, Computer Organization and Architecture, 5th Edition, Prentice-Hall, 2000. ftp://ftp.prenhall.com/pub/esm/computer_s cience.s-041/stallings/Slides/COA5eSlides/ IA-32 Intel Architecture Software Developers Manual Volume 1: Basic Architecture http://www.intel.com/home/pentium4/

S. Mandayam/ CompArch2/ECE Dept./Rowan University

Summary

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