Scribd
Upload
31 views1 page

EEE 51 Assignment 1: S Max

This document contains instructions for three assignments on diode and transistor modeling: 1. Model a pn-junction diode as a simple circuit with a cut-in voltage Vj and resistance RD, such that the model matches the real diode's I-V curve. Determine Vj and RD that minimize error between the curves. 2. Plot the junction capacitance Cj of a silicon diode versus voltage for a step junction, graded junction, and beyond the junction voltage Vj. 3. Sketch the collector current IC versus collector-emitter voltage VCE characteristics of an npn transistor in the forward-active region for different base currents IB.

Uploaded by

countershadow_14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
31 views1 page

EEE 51 Assignment 1: S Max

This document contains instructions for three assignments on diode and transistor modeling: 1. Model a pn-junction diode as a simple circuit with a cut-in voltage Vj and resistance RD, such that the model matches the real diode's I-V curve. Determine Vj and RD that minimize error between the curves. 2. Plot the junction capacitance Cj of a silicon diode versus voltage for a step junction, graded junction, and beyond the junction voltage Vj. 3. Sketch the collector current IC versus collector-emitter voltage VCE characteristics of an npn transistor in the forward-active region for different base currents IB.

Uploaded by

countershadow_14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

EEE 51 Assignment 1

WFX 2nd Semester SY 2010 - 2011 Due: 5pm Friday, November 26, 2010 (Rm 201) 1. You are given a pn -junction diode with saturation current IS , and ideality factor , that is operated at temperature T (in Kelvin). The voltage across the diode is varied from 0 to Vmax . In order to be able to use this diode in a circuit you are building, you decide to create a simple model that contains only two parameters: (1) the diode cut-in voltage, Vj and (2) the eective ON resistance, RD . (a) What is the value of Vj and RD if you constrain the model such that both the diode current ID and its derivative, ID VD , is the same for both the real diode and your model (ID = ID,model ) at Vmax , where Vmax > Vj . (b) Given IS = 1A, = 2, T = 300K , and Vmax = 0.8V , plot the V-I characteristic of the diode and your model on the same linear axes. (c) Plot the V-I characteristic of the diode and your mode, this time using a logarithmic scale on the y-axis. (d) Plot the current error between the diode current and your model (I = ID ID,model ). What is the maximum error? What is the average error from 0 to Vmax ? (e) Bonus : Can you create a better model by varying Vj and RD , such that the average error is smaller? (+10% bonus on this assignment for the model with the smallest average error) 2. A silicon diode with a step junction has a zero-bias capacitance Cj 0 . (a) Plot the diode junction capacitance as a function of the voltage across the diode, VD , assuming VBR < VD < Vj . (b) Plot the diode junction capacitance assuming that the diode has a graded pn -junction. (c) What happens to the capacitance as VD is increased beyond Vj ? 3. Given an npn transistor with F = 100 (measured at low VCE ), VA = 50, BVCB 0 = 120V , and n = 4. Use IC = M F 1 CE 1+ V n. VCB VA 1M F IB and M =
1
BVCB 0

(a) Sketch the IC -VCE characteristics in the forward-active region of the transistor with IC from 0 to 10mA and VCE from 0 to 50V. Use IB = 1A, 10A, 30A, and 60A. (b) Repeat part (a) with VCE from 0 to 10V.

You might also like