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Half Subtractor VHDL Code Using Behavioural Modeling

The document describes a VHDL code for a half subtractor using behavioral modeling. It defines the entity with input ports a and b and output ports diff and borrow. The architecture contains a process that models the half subtractor logic. If a is 0, it sets diff to b and borrow to b. Otherwise it sets diff to the inverse of b and borrow to 0, following the truth table for a half subtractor.

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7K views

Half Subtractor VHDL Code Using Behavioural Modeling

The document describes a VHDL code for a half subtractor using behavioral modeling. It defines the entity with input ports a and b and output ports diff and borrow. The architecture contains a process that models the half subtractor logic. If a is 0, it sets diff to b and borrow to b. Otherwise it sets diff to the inverse of b and borrow to 0, following the truth table for a half subtractor.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING BEHAVIOURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic (predefined data type).

entity half_subtractor is Port ( a, b: in STD_LOGIC; diff ,borrow: out STD_LOGIC); end half_subtractor; --------------------------------------------architecture Behavioral_HS of half_subtractor is begin ------------------------------process (a,b) begin if(a='0') then diff<=b; borrow <= b; else diff<= not b; borrow<= '0'; end if; end process; --------------------------------end Behavioral_HS;

Entity declaration. a, b :- input port bits (bits to be added) Sum, carry:- output port bits

Process statements (sensitivity list) Behavioral representation of half adder... Truth table:-

A 0 0 1 1

B 0 1 0 1

Sum 0 1 1 0

Borrow 0 1 0 0

RTL VIEW:-

OUT PUT WAVEFORMS:-

INFOOP2R.WIX.COM/OP2R

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