Half Adder VHDL Code Using Structrucral Modeling

This document contains the VHDL code for a half subtractor using structural modeling. It defines the entity and architecture for a half subtractor with two inputs (a and b) and two outputs (sum and carry). The architecture instantiates xor_1 and and_1 components which are connected to perform the half subtractor logic. The code maps the component ports to the entity ports to implement the half subtractor circuit structure and behavior.

Uploaded by

OP2R

Available Formats

Download as PDF, TXT or read online on Scribd

100% found this document useful (2 votes)

8K views

Half Adder VHDL Code Using Structrucral Modeling

Uploaded by

OP2R

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 1

INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164. package for std_logic (predefined data types).

entity half_adder is Port ( a, b: in STD_LOGIC; sum ,carry: out STD_LOGIC); end half_adder; --------------------------------------------architecture Behavioral of half_adder is ---------------------------------------------component xor_1 is Port ( o,p : in STD_LOGIC; q : out STD_LOGIC); end component; component and_1 is Port ( x,y : in STD_LOGIC; z : out STD_LOGIC); end component; ----------------------------------------------begin X1: xor_1 port map (a, b, sum); x2: and_1 port map (a, b, carry); end Behavioral; -----------------------------------------------

Entity declaration. a, b: - input port bits (bits to be added) sum, carry: - output port bits

Component (Ex-or, And, Not) declaration. These components are describing the structure view of half adder.

Architecture statements part (Architecture body). Components are port mapped to perform the circuit (adder) operation.

RTL VIEW:-

OUT PUT WAVEFORMS:-

INFOOP2R.WIX.COM/OP2R

IEEE-754 Floating Point Multipler in Verilog
55% (11)
IEEE-754 Floating Point Multipler in Verilog
8 pages
Array Multiplier 8x8 Verilog Code
0% (1)
Array Multiplier 8x8 Verilog Code
5 pages
SR - To - T Flip Flop Conversion VHDL Code
No ratings yet
SR - To - T Flip Flop Conversion VHDL Code
2 pages
J-K - To - D Flip-Flop Conversion VHDL Code
No ratings yet
J-K - To - D Flip-Flop Conversion VHDL Code
2 pages
VHDL Code For 4-Bit Shift Register
50% (2)
VHDL Code For 4-Bit Shift Register
3 pages
Tanner Tools Tutorial PDF
No ratings yet
Tanner Tools Tutorial PDF
115 pages
VHDL MCQ
100% (2)
VHDL MCQ
35 pages
Amplitude Modulation: Matlab Code
No ratings yet
Amplitude Modulation: Matlab Code
14 pages
Half Subtractor VHDL Code Using Behavioural Modeling
No ratings yet
Half Subtractor VHDL Code Using Behavioural Modeling
1 page
Full Adder VHDL Code Using Structural Modeling
91% (11)
Full Adder VHDL Code Using Structural Modeling
2 pages
Full Subtractor VHDL Code Using Data Flow Modeling
100% (1)
Full Subtractor VHDL Code Using Data Flow Modeling
1 page
Half Adder VHDL Code Using Dataflow Modeling
No ratings yet
Half Adder VHDL Code Using Dataflow Modeling
1 page
Full Subtractor VHDL Code Using Structural Modeling
No ratings yet
Full Subtractor VHDL Code Using Structural Modeling
2 pages
Half Subtractor VHDL Code Using Structrucral Modeling
0% (3)
Half Subtractor VHDL Code Using Structrucral Modeling
2 pages
Full Adder VHDL Code Using Data Flow Modeling
No ratings yet
Full Adder VHDL Code Using Data Flow Modeling
1 page
Half Adder VHDL Code Using Behavioural Modeling
100% (5)
Half Adder VHDL Code Using Behavioural Modeling
1 page
S-R Flip Flop Using Behavioural Modeling
No ratings yet
S-R Flip Flop Using Behavioural Modeling
2 pages
D Flip Flop - Structural Modeling
No ratings yet
D Flip Flop - Structural Modeling
2 pages
J-K Flip Flop Usig Behavioural Modeling
No ratings yet
J-K Flip Flop Usig Behavioural Modeling
2 pages
Half Subtractor VHDL Code Using Dataflow Modeling
No ratings yet
Half Subtractor VHDL Code Using Dataflow Modeling
1 page
Ripple Carry Adder VHDL Code Using Structural Modelling
0% (1)
Ripple Carry Adder VHDL Code Using Structural Modelling
1 page
T Flip-Flop VHDL Code Using Behavioural Modeling
100% (1)
T Flip-Flop VHDL Code Using Behavioural Modeling
2 pages
Xor Gate Beha - Modeling
No ratings yet
Xor Gate Beha - Modeling
1 page
Decoder VHDL Code Using Behavioural Flow Modeling
No ratings yet
Decoder VHDL Code Using Behavioural Flow Modeling
1 page
2's Complement VHDL Code Using Structrucral Modeling
No ratings yet
2's Complement VHDL Code Using Structrucral Modeling
2 pages
D - To - J-K Flip Flop Conversion VHDL Code
No ratings yet
D - To - J-K Flip Flop Conversion VHDL Code
2 pages
Binary To Excess 3 VHDL Code Using Structural Modeling
No ratings yet
Binary To Excess 3 VHDL Code Using Structural Modeling
1 page
SR - To - JK Flip Flop Conversion VHDL Code
No ratings yet
SR - To - JK Flip Flop Conversion VHDL Code
2 pages
NAND Gate Beh - Modeling
No ratings yet
NAND Gate Beh - Modeling
1 page
2's Complement VHDL Code Using Data Flow Modeling
67% (3)
2's Complement VHDL Code Using Data Flow Modeling
1 page
VHDL Code For Half Adder by Data Flow Modelling
96% (24)
VHDL Code For Half Adder by Data Flow Modelling
14 pages
Serial Binary Adder
No ratings yet
Serial Binary Adder
16 pages
Linear Convolution Program in C Language Using CCStudio
80% (5)
Linear Convolution Program in C Language Using CCStudio
3 pages
Logic Gates Using Dataflow Modeling
100% (3)
Logic Gates Using Dataflow Modeling
2 pages
VHDL Code For Serial in Serial Out Shift Register Using Behavioral Modelling
86% (7)
VHDL Code For Serial in Serial Out Shift Register Using Behavioral Modelling
3 pages
VHDL Code For 4 Bit Comparator
44% (9)
VHDL Code For 4 Bit Comparator
2 pages
Full Adder Using 4x1 Mux
100% (1)
Full Adder Using 4x1 Mux
3 pages
Half and Full Adder Using VHDL
100% (3)
Half and Full Adder Using VHDL
16 pages
Decade Counter
100% (3)
Decade Counter
2 pages
Expt 4. 16x1 Mux Using 4x1 Mux
67% (3)
Expt 4. 16x1 Mux Using 4x1 Mux
6 pages
Half Subtractor Half Subtractor - Gate Level Modelling
No ratings yet
Half Subtractor Half Subtractor - Gate Level Modelling
10 pages
VHDL Code For 1 To 4 Demux
No ratings yet
VHDL Code For 1 To 4 Demux
6 pages
VHDL 4 To 1 Mux (Multiplexer)
No ratings yet
VHDL 4 To 1 Mux (Multiplexer)
9 pages
AIM: - Write A VHDL Code For 4 Bit Ripple Carry Adder Using Loop Statement. Code
No ratings yet
AIM: - Write A VHDL Code For 4 Bit Ripple Carry Adder Using Loop Statement. Code
4 pages
Exam1 (Example With Solutions)
100% (2)
Exam1 (Example With Solutions)
5 pages
SIPO Register VHDL Code With Testbench
100% (1)
SIPO Register VHDL Code With Testbench
2 pages
Verilog Code For Vending Machine: BY D Meghana
No ratings yet
Verilog Code For Vending Machine: BY D Meghana
22 pages
VHDL Code For 1 Bit Comparator by Data Flow Modelling, Structural Modelling and Behavioural Modelling
No ratings yet
VHDL Code For 1 Bit Comparator by Data Flow Modelling, Structural Modelling and Behavioural Modelling
10 pages
Verilog Codes For Combinational Ciruits Along With Their Test Bench
100% (1)
Verilog Codes For Combinational Ciruits Along With Their Test Bench
28 pages
TDM
No ratings yet
TDM
4 pages
Question Paper With Solution - The 8051 Microcontroller Based Embedded SystemsJUNE - JULY 2013 VTU
100% (2)
Question Paper With Solution - The 8051 Microcontroller Based Embedded SystemsJUNE - JULY 2013 VTU
29 pages
Hamming Code Matlab
0% (1)
Hamming Code Matlab
3 pages
8086 Full Full Notes of Microprocessor
No ratings yet
8086 Full Full Notes of Microprocessor
75 pages
Verilog HDL Code For Y A'B+C'D'
No ratings yet
Verilog HDL Code For Y A'B+C'D'
48 pages
P N Junction Theory and Diodes Part II - GATE Problems 001
No ratings yet
P N Junction Theory and Diodes Part II - GATE Problems 001
32 pages
Construction of Reflex Klystron
100% (1)
Construction of Reflex Klystron
3 pages
Passive Impedance Transformation
100% (1)
Passive Impedance Transformation
11 pages
XILINX XC Series
100% (1)
XILINX XC Series
41 pages
Verilog HDL Lab Manual
No ratings yet
Verilog HDL Lab Manual
136 pages
1's Complement VHDL Code Using Dataflow Modeling
No ratings yet
1's Complement VHDL Code Using Dataflow Modeling
1 page
1's Complement VHDL Code Using Structrucral Modeling
No ratings yet
1's Complement VHDL Code Using Structrucral Modeling
1 page
Binary To Gray Converter VHDL Code Using Structural Modeling
67% (3)
Binary To Gray Converter VHDL Code Using Structural Modeling
1 page
OR Gate Beha - Modeling
No ratings yet
OR Gate Beha - Modeling
1 page
Demux VHDL Code Using Behavioural Modeling
No ratings yet
Demux VHDL Code Using Behavioural Modeling
1 page
Xnor Gate Beha - Modeling
No ratings yet
Xnor Gate Beha - Modeling
1 page
NOR Gate Beha - Modeling
No ratings yet
NOR Gate Beha - Modeling
1 page
And Gate Beh - Modeling
No ratings yet
And Gate Beh - Modeling
1 page