Scribd
Upload
8K views

Half Adder VHDL Code Using Structrucral Modeling

This document contains the VHDL code for a half subtractor using structural modeling. It defines the entity and architecture for a half subtractor with two inputs (a and b) and two outputs (sum and carry). The architecture instantiates xor_1 and and_1 components which are connected to perform the half subtractor logic. The code maps the component ports to the entity ports to implement the half subtractor circuit structure and behavior.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
8K views

Half Adder VHDL Code Using Structrucral Modeling

This document contains the VHDL code for a half subtractor using structural modeling. It defines the entity and architecture for a half subtractor with two inputs (a and b) and two outputs (sum and carry). The architecture instantiates xor_1 and and_1 components which are connected to perform the half subtractor logic. The code maps the component ports to the entity ports to implement the half subtractor circuit structure and behavior.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164. package for std_logic (predefined data types).

entity half_adder is Port ( a, b: in STD_LOGIC; sum ,carry: out STD_LOGIC); end half_adder; --------------------------------------------architecture Behavioral of half_adder is ---------------------------------------------component xor_1 is Port ( o,p : in STD_LOGIC; q : out STD_LOGIC); end component; component and_1 is Port ( x,y : in STD_LOGIC; z : out STD_LOGIC); end component; ----------------------------------------------begin X1: xor_1 port map (a, b, sum); x2: and_1 port map (a, b, carry); end Behavioral; -----------------------------------------------

Entity declaration. a, b: - input port bits (bits to be added) sum, carry: - output port bits

Component (Ex-or, And, Not) declaration. These components are describing the structure view of half adder.

Architecture statements part (Architecture body). Components are port mapped to perform the circuit (adder) operation.

RTL VIEW:-

OUT PUT WAVEFORMS:-

INFOOP2R.WIX.COM/OP2R

You might also like