Scribd
Upload
18K views

Full Adder VHDL Code Using Structural Modeling

The document contains VHDL code for implementing a full adder using structural modeling. It first declares library and package components needed. It then defines the entity with input and output ports. The architecture section declares internal signals and instantiates components like XOR, AND and OR gates. It then maps the ports of these components to perform the full adder operation. The code structurally models the full adder circuit using basic logic gates.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
18K views

Full Adder VHDL Code Using Structural Modeling

The document contains VHDL code for implementing a full adder using structural modeling. It first declares library and package components needed. It then defines the entity with input and output ports. The architecture section declares internal signals and instantiates components like XOR, AND and OR gates. It then maps the ports of these components to perform the full adder operation. The code structurally models the full adder circuit using basic logic gates.

Uploaded by

OP2R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

FULL ADDER VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic predefined data type.

entity full_adder is Port ( a, b, c: in STD_LOGIC; sum ,carry: out STD_LOGIC); end full_adder; --------------------------------------------architecture Behavioral_FA of full_adder is ------------------------------------------------signal c1, c2, c3: in std_logic; component xor_2 is port (k,d,e: in std_logic; f: out std_logic); end component; component and_1 is Port ( x,y : in STD_LOGIC; z : out STD_LOGIC); end component; component or_1 is Port ( g,h,i : in STD_LOGIC; z : out STD_LOGIC); end component; ----------------------------------------------begin X0: xor_2 port map (a,b,c, sum); X2: and_1 port map (a,b,c1); X3: and_1 port map (a,b,c2); X4: and_1 port map (a,b,c3); x5: or_1 port map (c1, c2, c3, carry); -------------------------------------------------end Behavioral_FA;

Entity declaration. a, b, c :- input port bits (bits to be added) Sum, carry:- output port bits

Signal declaration. C1,c2,c3 signals will act as inout port. Component (Ex-or, and, or) declaration. Declarative part of full adders Architecture. Components represent the structure of full adder circuit.

Statements part of the architecture. Components are port mapped to perform full adder operation.

INFOOP2R.WIX.COM/OP2R

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

RTL VIEW:-

OUT PUT WAVEFORMS:

INFOOP2R.WIX.COM/OP2R

You might also like