Binary To Gray Converter VHDL Code Using Structural Modeling

This document describes a VHDL code for converting binary to gray code using structural modeling. It defines an entity with input and output ports for the binary and gray codes. The architecture contains a component declaration for an XOR gate and maps the input and output ports of multiple instances of this component to perform the binary to gray code conversion. The code implements the conversion through a cascade of XOR gates connecting the binary input bits to the gray code output bits.

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Binary To Gray Converter VHDL Code Using Structural Modeling

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

BINARY TO GRAY CODE CONVERSION

VHDL CODE USING STRUCTURAL MODELING

Library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity B_G is
Port ( bin: in std_logic_vector (1 downto 0 );
gray: out std_logic_vector (3 downto 0);
end B_G;

Std_logic_1164. package for std_logic (predefined data type).

Entity declaration.
bin :- input port bits.(code that will be
converted in to its equivalent gray
representation.)
gray: - output port bits. (Converted code)

---------------------------------------------------------architecture Behavioral_BG of B_G is

---------------------------------------------component xor_1 is
Port ( o,p : in STD_LOGIC;
q : out STD_LOGIC);
end component;
---------------------------------------------------------begin
l1: xor_1 port map (bin(3), 0, gray(3));
l2: xor_1 port map (bin(3), bin(2),gray(2));
l3: xor_1 port map (bin(2), bin(1),gray(1));
l4: xor_1 port map (bin(1), bin(0),gray(0));
---------------------------------------------------------end Behavioral_BG;

RTL VIEW:-

INFOOP2R.WIX.COM/OP2R

OUT PUT WAVEFORMS

Component declarative part of

architecture.
Component xor_1 is declared which is
acting as an EX-OR gate.

Statement part of architecture.

Declared components (in
statement part) ports are mapped
to perform the circuit operation.

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Binary To Gray Converter VHDL Code Using Structural Modeling

Uploaded by

Binary To Gray Converter VHDL Code Using Structural Modeling

Uploaded by

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

BINARY TO GRAY CODE CONVERSION

Std_logic_1164. package for std_logic (predefined data type).

---------------------------------------------------------architecture Behavioral_BG of B_G is

OUT PUT WAVEFORMS

Component declarative part of

Statement part of architecture.

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