Binary To Excess 3 VHDL Code Using Structural Modeling

This document describes a VHDL code for converting binary codes to excess-3 code. It defines an entity with input and output ports for the binary and excess-3 codes. The architecture contains signal declarations for inverted binary bits and uses Boolean logic operations to assign the excess-3 code bits based on combinations of the binary input bits. Simulation waveforms are shown to verify the code converts the binary inputs to the correct excess-3 code outputs.

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Binary To Excess 3 VHDL Code Using Structural Modeling

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

BINARY TO EXCESS 3 CODE CONVERSIONS

VHDL CODE USING STRUCTURAL MODELING

Library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity B_xcess is
Port ( bin: in std_logic_vector (1 downto 0 );
exss: out std_logic_vector (3 downto 0);
end B_xcess;

Std_logic_1164. package for std_logic (predefined data type).

Entity declaration.
bin :- input port bits.(code that will be
converted in to its equivalent excess 3
representation.)
exss: - output port bits. (Converted code).

---------------------------------------------------------architecture Behavioral_bxcess of B_xcess is

----------------------------------------------------------signal bin0bar, bin1bar, bin2bar: std_logic;

Architectures declarative part.

Three signals are declared here. These signals
will act as inout ports.

------------------------------------------------------------------begin
bin2bar<= not bin(2);
bin1bar<= not bin(1);
bin0bar<= not bin(0);
xcess(3)<= (bin(3) and (bin(2)and(bin(0) or bin(1))));
xcess(2)<= ((bin2bar and (bin(1)or bin(0))) or
(bin(2)and bin1bar and bin0bar));
xcess(1)<= bin(1) xnor bin(0);
xcess(0)<= not bin(0);
end Behavioral_binexss;
-------------------------------------------------------------------end Behavioral_bxcess;

RTL VIEW:-

INFOOP2R.WIX.COM/OP2R

OUT PUT WAVEFORMS

Architectures statement part.

These are the concurrent
statements which will be
executed in random order.
These are the statements which
we have got after solving the
circuit by using k-map and
Boolean algebra.

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Binary To Excess 3 VHDL Code Using Structural Modeling

Uploaded by

Binary To Excess 3 VHDL Code Using Structural Modeling

Uploaded by

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

BINARY TO EXCESS 3 CODE CONVERSIONS

Std_logic_1164. package for std_logic (predefined data type).

---------------------------------------------------------architecture Behavioral_bxcess of B_xcess is

Architectures declarative part.

OUT PUT WAVEFORMS

Architectures statement part.

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