2's Complement VHDL Code Using Structrucral Modeling

The document describes a VHDL code for implementing two's complement using a structural modeling approach. It defines the entity with input, enable, and output ports. It then defines components for XOR gates and half adders used to perform the two's complement operation. The architecture maps the components to temporarily store the one's complement result before the half adders add 1 to produce the two's complement output value.

Uploaded by

OP2R

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

1K views2 pages

2's Complement VHDL Code Using Structrucral Modeling

Uploaded by

OP2R

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

TWOS COMPLEMENT VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL;

Std_logic_1164. package for std_logic (predefined data types).

-----------------------------------------------------------------entity twos_comp is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); e : in STD_LOGIC; z : out STD_LOGIC_VECTOR (3 downto 0)); end twos_comp; -----------------------------------------------------------------architecture Behavioral_2scomp of twos_comp is -----------------------------------------------component xor_1 is Port ( o,p : in STD_LOGIC; q : out STD_LOGIC); end component; component half_adder is Port ( a, b: in STD_LOGIC; sum ,carry: out STD_LOGIC); end component; -------------------------------------------------------------begin x1: xor_1 port map (i(0),e,temp(0)); x2: xor_1 port map (i(1),e,temp(1)); x3: xor_1 port map (i(2),e,temp(2)); x4: xor_1 port map (i(3),e,temp(3)); x5: half_adder port map (temp(0),'1',s(0),c(0)); x6: half_adder port map (temp(1),c(0),s(1),c(1)); x7: half_adder port map (temp(2),c(1),s(2),c(2)); x8: half_adder port map (temp(3),c(2),s(3),c(3)); z<= s; ---------------------------------------------------------------end Behavioral_2scomp;

Entity declaration. i: - input port bits. e: - enable pin. If e=1 circuit will produce twos complement. z: - output port bits.(2s complement of input).

Component (Ex-or, half adder) declaration. These components are describing the structural view of twos complement circuit.

Architecture statements part (Architecture body). Components are port mapped to perform the circuit (2s complement) operation. Ex-or gate is responsible for 1s complement. Ones complement result is temporarily stored is temp signal. Then half adder will add 1 to form twos complement. Half adder sum will be assigned to output z.

[Link]/OP2R

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

RTL VIEW:-

OUT PUT WAVEFORMS:-

[Link]/OP2R

1's Complement VHDL Code Using Structrucral Modeling
No ratings yet
1's Complement VHDL Code Using Structrucral Modeling
1 page
Full Adder VHDL Code Using Structural Modeling
91% (11)
Full Adder VHDL Code Using Structural Modeling
2 pages
2's Complement VHDL Code Using Data Flow Modeling
67% (3)
2's Complement VHDL Code Using Data Flow Modeling
1 page
Full Subtractor VHDL Code Using Structural Modeling
No ratings yet
Full Subtractor VHDL Code Using Structural Modeling
2 pages
1's Complement VHDL Code Using Dataflow Modeling
No ratings yet
1's Complement VHDL Code Using Dataflow Modeling
1 page
Half Subtractor VHDL Code Using Structrucral Modeling
0% (3)
Half Subtractor VHDL Code Using Structrucral Modeling
2 pages
D Flip Flop - Structural Modeling
No ratings yet
D Flip Flop - Structural Modeling
2 pages
VHDL Project
No ratings yet
VHDL Project
14 pages
VHDL Design for Logic Gates & Adders
No ratings yet
VHDL Design for Logic Gates & Adders
61 pages
Ripple Carry Adder VHDL Code Using Structural Modelling
0% (1)
Ripple Carry Adder VHDL Code Using Structural Modelling
1 page
Half Adder VHDL Code Using Structrucral Modeling
100% (2)
Half Adder VHDL Code Using Structrucral Modeling
1 page
VHDL Half Subtractor Guide
No ratings yet
VHDL Half Subtractor Guide
1 page
Design A Half Adder Using Dataflow Architecture in VHDL Code (Autorecovered)
No ratings yet
Design A Half Adder Using Dataflow Architecture in VHDL Code (Autorecovered)
14 pages
ContohVHDL PartI II Tugas
No ratings yet
ContohVHDL PartI II Tugas
55 pages
VHDL Sumador y Decodificador
No ratings yet
VHDL Sumador y Decodificador
18 pages
Vlsi 8
No ratings yet
Vlsi 8
17 pages
Ee529 Lab Asg
No ratings yet
Ee529 Lab Asg
11 pages
UNIT-3: Design Combinational CKT Using Architecture Model
No ratings yet
UNIT-3: Design Combinational CKT Using Architecture Model
36 pages
Half Adder Structural Model
No ratings yet
Half Adder Structural Model
4 pages
TD Digital Synthesis of Basic Component Using VHDL-Enoncé+Solution
No ratings yet
TD Digital Synthesis of Basic Component Using VHDL-Enoncé+Solution
10 pages
Vlsi Lab Pgms
No ratings yet
Vlsi Lab Pgms
18 pages
Exp 4vlsi
No ratings yet
Exp 4vlsi
9 pages
Using VHDL To Describe Adders
No ratings yet
Using VHDL To Describe Adders
8 pages
stRUCTURAL mODELING OF fULL aDDER
No ratings yet
stRUCTURAL mODELING OF fULL aDDER
8 pages
VHDL Code for Adders and Multiplexers
No ratings yet
VHDL Code for Adders and Multiplexers
30 pages
Prgms From Report
No ratings yet
Prgms From Report
54 pages
VHDL Revaluation Report
No ratings yet
VHDL Revaluation Report
5 pages
VHDL Design and Simulation Guide
No ratings yet
VHDL Design and Simulation Guide
20 pages
Rogram No: 1 AIM: Write HDL Code To Realize All The Logic Gates
No ratings yet
Rogram No: 1 AIM: Write HDL Code To Realize All The Logic Gates
32 pages
VHDL & Verilog Circuit Designs
No ratings yet
VHDL & Verilog Circuit Designs
66 pages
Exp - No: 1 Basic Gates Date: 30.01.10 - Aim
No ratings yet
Exp - No: 1 Basic Gates Date: 30.01.10 - Aim
31 pages
Half Adder Component Implementation
No ratings yet
Half Adder Component Implementation
1 page
4-Bit Adder/Subtractor Design in VHDL
100% (33)
4-Bit Adder/Subtractor Design in VHDL
85 pages
Full Adder VHDL Code Using Data Flow Modeling
No ratings yet
Full Adder VHDL Code Using Data Flow Modeling
1 page
Digital System Design Lab Experiments
No ratings yet
Digital System Design Lab Experiments
47 pages
VHDL Code For BEHAVIORAL Model of Full Adder
No ratings yet
VHDL Code For BEHAVIORAL Model of Full Adder
2 pages
Combinational Circuit Design Lab Guide
No ratings yet
Combinational Circuit Design Lab Guide
62 pages
VHDL Program
No ratings yet
VHDL Program
5 pages
Adder Compo
No ratings yet
Adder Compo
4 pages
4bit Adder Project Final
No ratings yet
4bit Adder Project Final
4 pages
Combinational Circuit1
No ratings yet
Combinational Circuit1
7 pages
Department of Electronics Engineering: Experiment No: 1 Title
No ratings yet
Department of Electronics Engineering: Experiment No: 1 Title
11 pages
VHDL Full Adder Using NAND Gates
100% (1)
VHDL Full Adder Using NAND Gates
49 pages
VLSI Lab
No ratings yet
VLSI Lab
21 pages
VHDL Digital Circuit Design Examples
No ratings yet
VHDL Digital Circuit Design Examples
21 pages
Half Adder VHDL Code Using Dataflow Modeling
100% (1)
Half Adder VHDL Code Using Dataflow Modeling
1 page
Dcs File With Output (BPIT)
No ratings yet
Dcs File With Output (BPIT)
35 pages
Due Date: 10/07/15 1. Write The VHDL Text For The 2-Bit Magnitude Comparator Shown Below
No ratings yet
Due Date: 10/07/15 1. Write The VHDL Text For The 2-Bit Magnitude Comparator Shown Below
3 pages
DSD Lab Report
No ratings yet
DSD Lab Report
70 pages
A4 Coa 2021itb050
No ratings yet
A4 Coa 2021itb050
9 pages
Experiment2 - Coa Lab - 013
No ratings yet
Experiment2 - Coa Lab - 013
6 pages
Half Subtractor VHDL Code Using Dataflow Modeling
No ratings yet
Half Subtractor VHDL Code Using Dataflow Modeling
1 page
Full Subtractor VHDL Code Using Data Flow Modeling
100% (1)
Full Subtractor VHDL Code Using Data Flow Modeling
1 page
Half Subtractor VHDL Code Using Behavioural Modeling
No ratings yet
Half Subtractor VHDL Code Using Behavioural Modeling
1 page
Half Adder VHDL Code Using Behavioural Modeling
100% (5)
Half Adder VHDL Code Using Behavioural Modeling
1 page
VHDL Structural Model for Excess-3 Code
No ratings yet
VHDL Structural Model for Excess-3 Code
1 page
Binary To Gray Converter VHDL Code Using Structural Modeling
67% (3)
Binary To Gray Converter VHDL Code Using Structural Modeling
1 page
Demux VHDL Code Using Behavioural Modeling
No ratings yet
Demux VHDL Code Using Behavioural Modeling
1 page
VHDL Decoder Code with Behavioral Modeling
No ratings yet
VHDL Decoder Code with Behavioral Modeling
1 page
VHDL Code for EX-OR Gate Design
No ratings yet
VHDL Code for EX-OR Gate Design
1 page
VHDL Behavioral Modeling for OR Gate
No ratings yet
VHDL Behavioral Modeling for OR Gate
1 page
VHDL Code for XNOR Gate
No ratings yet
VHDL Code for XNOR Gate
1 page
And Gate Beh - Modeling
No ratings yet
And Gate Beh - Modeling
1 page
SR - To - JK Flip Flop Conversion VHDL Code
No ratings yet
SR - To - JK Flip Flop Conversion VHDL Code
2 pages
J-K Flip Flop Usig Behavioural Modeling
No ratings yet
J-K Flip Flop Usig Behavioural Modeling
2 pages
NOR Gate Beha - Modeling
No ratings yet
NOR Gate Beha - Modeling
1 page
VHDL Code for NAND Gate Modeling
No ratings yet
VHDL Code for NAND Gate Modeling
1 page
SR - To - T Flip Flop Conversion VHDL Code
No ratings yet
SR - To - T Flip Flop Conversion VHDL Code
2 pages
S-R Flip Flop Using Behavioural Modeling
No ratings yet
S-R Flip Flop Using Behavioural Modeling
2 pages
T Flip-Flop VHDL Code Using Behavioural Modeling
100% (1)
T Flip-Flop VHDL Code Using Behavioural Modeling
2 pages
J-K - To - D Flip-Flop Conversion VHDL Code
No ratings yet
J-K - To - D Flip-Flop Conversion VHDL Code
2 pages