NAND Gate Beh - Modeling

This document describes VHDL code for a 2-input NAND gate using behavioral modeling. The code defines an entity with inputs i and j and output k. The architecture contains a process that sets the output k to the logical NAND of the inputs i and j based on a truth table. When executed, this code will model the functionality of a 2-input NAND gate.

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NAND Gate Beh - Modeling

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) NAND GATE VHDL CODE USING BEHAVIOURAL MODELING library

IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------------------------entity nand_1 is Port ( i, j : in STD_LOGIC; *\\ i and j are the input port to the and gate. k : out STD_LOGIC); *\\ k is output port to the and gate. end nand_1; -----------------------------------------------------------architecture Behavioural_nand of nand_1 is begin *\\ architecture of nand_1 entity begins. --------------process(i, j) *\\ process (sensitivity list). After this statement all statement will be executed in sequence. begin if (j='1') then *\\ if (condition is true then ) output (k) equal to not of i. k<= not i; else *\\ otherwise output (k) equal to 1. k<='1'; end if; end process; ----------------end Behavioural_nand; *\\ end the architecture. TRUTH TABLE: -

OUTPUT WAVEFORM: -

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NAND Gate Beh - Modeling

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NAND Gate Beh - Modeling

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) NAND GATE VHDL CODE USING BEHAVIOURAL MODELING library

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