NAND Gate Beh - Modeling

This document describes VHDL code for a 2-input NAND gate using behavioral modeling. The code defines an entity with inputs i and j and output k. The architecture contains a process that sets the output k to the logical NAND of the inputs i and j based on a truth table. When executed, this code will model the functionality of a 2-input NAND gate.

Uploaded by

OP2R

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

119 views1 page

NAND Gate Beh - Modeling

Uploaded by

OP2R

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 1

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) NAND GATE VHDL CODE USING BEHAVIOURAL MODELING library

IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------------------------entity nand_1 is Port ( i, j : in STD_LOGIC; *\\ i and j are the input port to the and gate. k : out STD_LOGIC); *\\ k is output port to the and gate. end nand_1; -----------------------------------------------------------architecture Behavioural_nand of nand_1 is begin *\\ architecture of nand_1 entity begins. --------------process(i, j) *\\ process (sensitivity list). After this statement all statement will be executed in sequence. begin if (j='1') then *\\ if (condition is true then ) output (k) equal to not of i. k<= not i; else *\\ otherwise output (k) equal to 1. k<='1'; end if; end process; ----------------end Behavioural_nand; *\\ end the architecture. TRUTH TABLE: -

OUTPUT WAVEFORM: -

INFOOP2R.WIX.COM/OP2R

SR - To - T Flip Flop Conversion VHDL Code
No ratings yet
SR - To - T Flip Flop Conversion VHDL Code
2 pages
J-K - To - D Flip-Flop Conversion VHDL Code
No ratings yet
J-K - To - D Flip-Flop Conversion VHDL Code
2 pages
VHDL Code For 4 Bit Multiplayer and Division
33% (3)
VHDL Code For 4 Bit Multiplayer and Division
5 pages
Solution Manual of Appendix A Exercise at (CMOS VLSI Design) by NEILL and Harris
100% (1)
Solution Manual of Appendix A Exercise at (CMOS VLSI Design) by NEILL and Harris
13 pages
Xor Gate Beha - Modeling
No ratings yet
Xor Gate Beha - Modeling
1 page
Xnor Gate Beha - Modeling
No ratings yet
Xnor Gate Beha - Modeling
1 page
Decoder VHDL Code Using Behavioural Flow Modeling
No ratings yet
Decoder VHDL Code Using Behavioural Flow Modeling
1 page
2's Complement VHDL Code Using Data Flow Modeling
67% (3)
2's Complement VHDL Code Using Data Flow Modeling
1 page
Half Subtractor VHDL Code Using Dataflow Modeling
No ratings yet
Half Subtractor VHDL Code Using Dataflow Modeling
1 page
Binary To Excess 3 VHDL Code Using Structural Modeling
No ratings yet
Binary To Excess 3 VHDL Code Using Structural Modeling
1 page
Half Adder VHDL Code Using Dataflow Modeling
No ratings yet
Half Adder VHDL Code Using Dataflow Modeling
1 page
Chapter 5 Synchronous Sequential Circuit
100% (1)
Chapter 5 Synchronous Sequential Circuit
32 pages
Binary To Gray Converter VHDL Code Using Structural Modeling
67% (3)
Binary To Gray Converter VHDL Code Using Structural Modeling
1 page
S-R Flip Flop Using Behavioural Modeling
No ratings yet
S-R Flip Flop Using Behavioural Modeling
2 pages
Ripple Carry Adder VHDL Code Using Structural Modelling
0% (1)
Ripple Carry Adder VHDL Code Using Structural Modelling
1 page
J-K Flip Flop Usig Behavioural Modeling
No ratings yet
J-K Flip Flop Usig Behavioural Modeling
2 pages
Book 002 LaMeres Logic Circuits W VHDL CoverNtoc
No ratings yet
Book 002 LaMeres Logic Circuits W VHDL CoverNtoc
15 pages
Assignment 05 Solution
No ratings yet
Assignment 05 Solution
8 pages
Smart Vehicle - To-Vehicle Communication With 5G Technology
No ratings yet
Smart Vehicle - To-Vehicle Communication With 5G Technology
4 pages
1's Complement VHDL Code Using Dataflow Modeling
No ratings yet
1's Complement VHDL Code Using Dataflow Modeling
1 page
Allprob 08 N 2
No ratings yet
Allprob 08 N 2
11 pages
Serial Binary Adder
No ratings yet
Serial Binary Adder
16 pages
Full Adder VHDL
No ratings yet
Full Adder VHDL
52 pages
D Flip Flop - Structural Modeling
No ratings yet
D Flip Flop - Structural Modeling
2 pages
VHDL Programs
100% (1)
VHDL Programs
30 pages
Experiment 4 PCM
No ratings yet
Experiment 4 PCM
5 pages
Half and Full Adder Using VHDL
100% (3)
Half and Full Adder Using VHDL
16 pages
Digital Logic Design: VHDL Coding For Fpgas Unit 5
No ratings yet
Digital Logic Design: VHDL Coding For Fpgas Unit 5
34 pages
Sirisha Kurakula G00831237 Project
0% (1)
Sirisha Kurakula G00831237 Project
12 pages
Compare Diffusion and Ion Implantation Sol: Diffusion Ion Implantation
No ratings yet
Compare Diffusion and Ion Implantation Sol: Diffusion Ion Implantation
12 pages
Booth Multiplier VHDL Code
50% (4)
Booth Multiplier VHDL Code
1 page
Full Subtractor VHDL Code Using Data Flow Modeling
100% (1)
Full Subtractor VHDL Code Using Data Flow Modeling
1 page
PID Tuning Cohen Coon Example
No ratings yet
PID Tuning Cohen Coon Example
8 pages
VHDL Exam
No ratings yet
VHDL Exam
2 pages
Test Bench For JK Flip
100% (2)
Test Bench For JK Flip
2 pages
8to1 Mux Using 4to1 Mux
100% (1)
8to1 Mux Using 4to1 Mux
5 pages
Chapter6b-Combinational Logic Design Practices
No ratings yet
Chapter6b-Combinational Logic Design Practices
38 pages
Acemoglu, Autor - 2011 - Skills, Tasks and Technologies Implications For Employment and Earnings
100% (1)
Acemoglu, Autor - 2011 - Skills, Tasks and Technologies Implications For Employment and Earnings
49 pages
L9 Understanding Atmega328P 2
100% (2)
L9 Understanding Atmega328P 2
15 pages
Verilog - PPT 1
No ratings yet
Verilog - PPT 1
41 pages
Digital Lab Cs 6211 VHDL Programs
No ratings yet
Digital Lab Cs 6211 VHDL Programs
13 pages
Full Adder VHDL Code Using Data Flow Modeling
No ratings yet
Full Adder VHDL Code Using Data Flow Modeling
1 page
VLSI Lab Manual
No ratings yet
VLSI Lab Manual
68 pages
Introduction To FPGA
No ratings yet
Introduction To FPGA
34 pages
VHDL ppt1
No ratings yet
VHDL ppt1
37 pages
Lab Manual With Procedure For Xilinx and Microwind
No ratings yet
Lab Manual With Procedure For Xilinx and Microwind
102 pages
VHDL Interfacing Programs
No ratings yet
VHDL Interfacing Programs
22 pages
VHDL Program
No ratings yet
VHDL Program
5 pages
Intall Archlinux Bootstrap
No ratings yet
Intall Archlinux Bootstrap
3 pages
Introduction To Cmos Vlsi Design: Circuits & Layout
No ratings yet
Introduction To Cmos Vlsi Design: Circuits & Layout
54 pages
Function Generator Using VHDL
No ratings yet
Function Generator Using VHDL
20 pages
Lab10 - Finite State Machines
No ratings yet
Lab10 - Finite State Machines
7 pages
Block Diagram Reduction Techniques
No ratings yet
Block Diagram Reduction Techniques
47 pages
VHDL Labmanual
100% (1)
VHDL Labmanual
27 pages
Design and Implementation of 64 Bit Alu Using VHDL
No ratings yet
Design and Implementation of 64 Bit Alu Using VHDL
59 pages
OR Gate Beha - Modeling
No ratings yet
OR Gate Beha - Modeling
1 page
NOR Gate Beha - Modeling
No ratings yet
NOR Gate Beha - Modeling
1 page
Ecad Lab Manual - Modified
100% (1)
Ecad Lab Manual - Modified
52 pages
And Gate Beh - Modeling
No ratings yet
And Gate Beh - Modeling
1 page
Ecad Lab Manual Pvpsit
No ratings yet
Ecad Lab Manual Pvpsit
53 pages
Half Subtractor VHDL Code Using Structrucral Modeling
0% (3)
Half Subtractor VHDL Code Using Structrucral Modeling
2 pages
Half Adder VHDL Code Using Structrucral Modeling
100% (2)
Half Adder VHDL Code Using Structrucral Modeling
1 page
Half Subtractor VHDL Code Using Behavioural Modeling
No ratings yet
Half Subtractor VHDL Code Using Behavioural Modeling
1 page
Half Adder VHDL Code Using Behavioural Modeling
100% (5)
Half Adder VHDL Code Using Behavioural Modeling
1 page
Full Subtractor VHDL Code Using Structural Modeling
No ratings yet
Full Subtractor VHDL Code Using Structural Modeling
2 pages
Full Adder VHDL Code Using Structural Modeling
91% (11)
Full Adder VHDL Code Using Structural Modeling
2 pages
Demux VHDL Code Using Behavioural Modeling
No ratings yet
Demux VHDL Code Using Behavioural Modeling
1 page
2's Complement VHDL Code Using Structrucral Modeling
No ratings yet
2's Complement VHDL Code Using Structrucral Modeling
2 pages
1's Complement VHDL Code Using Structrucral Modeling
No ratings yet
1's Complement VHDL Code Using Structrucral Modeling
1 page
SR - To - JK Flip Flop Conversion VHDL Code
No ratings yet
SR - To - JK Flip Flop Conversion VHDL Code
2 pages
T Flip-Flop VHDL Code Using Behavioural Modeling
100% (1)
T Flip-Flop VHDL Code Using Behavioural Modeling
2 pages

NAND Gate Beh - Modeling

Uploaded by

NAND Gate Beh - Modeling

Uploaded by

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) NAND GATE VHDL CODE USING BEHAVIOURAL MODELING library

You might also like